{ "schema_version": "1.3", "database_version": "2026.11.06-7", "registry_reviewed_at": "2026-11-06", "scope": "Curated public AI accelerator company and product registry. New and updated product claims are source-linked and classified as vendor-reported unless independently measured evidence is explicitly cited. Availability labels distinguish announced, shipping and production status. This revision adds reviewed, source-linked profiles for custom XPU suppliers and inference-focused accelerator companies; platform-level records are used where no public merchant SKU exists.", "freshness_policy": { "fresh_within_days": 90, "stale_after_days": 180, "missing_checked_at_means": "unreviewed", "notes": "Fresh means checked within 90 days; review due means 91–180 days; stale means older than 180 days. A missing checked_at is always unreviewed. Freshness describes source recency, not whether a claim is true." }, "profile_status_definitions": { "not_reviewed": "The directory profile is indexed, but no structured claim-level evidence audit has been completed.", "partially_reviewed": "Some products or claims have been structured and reviewed; profile coverage is incomplete.", "reviewed": "The currently published structured profile has been reviewed. Individual claims retain their own evidence status." }, "companies": [ { "id": "nvidia", "display_name": "NVIDIA — GPU / AI accelerator lineage", "category": "IC Vendors", "directory_anchor": "Nvidia", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Nvidia_logo.png", "summary": "NVIDIA turned GPUs into the default AI training/inference substrate via CUDA (2007) and successive datacenter architectures. From Pascal/Volta Tensor Cores through Ampere and Hopper, the stack evolved into rack-scale Grace+Blackwell systems; Rubin extends that AI-factory model into 2026.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [ { "id": "b200-sxm", "name": "NVIDIA B200 SXM", "product_type": "gpu", "architecture": "Blackwell", "generation": "Blackwell / B200", "market_segment": "Data-center AI training and inference", "availability": "shipping", "claim_ids": [ "b200-memory-capacity", "b200-memory-bandwidth", "b200-nvlink-bandwidth", "b200-architecture" ], "compatibility_platform_ids": [ "nvidia-gpu" ] }, { "id": "gb200-nvl72", "name": "NVIDIA GB200 NVL72", "product_type": "system", "architecture": "Grace Blackwell / Blackwell", "generation": "Blackwell / GB200", "family": "NVIDIA GB200", "market_segment": "Rack-scale AI training and inference", "availability": "shipping", "form_factor": "Liquid-cooled rack-scale system", "system_configuration": "36 Grace CPUs + 72 Blackwell GPUs; one 72-GPU NVLink domain", "notes": "System-level record. Aggregate rack specifications must not be compared directly with per-chip GPU specifications.", "claim_ids": [ "gb200-gpu-count", "gb200-hbm-capacity", "gb200-hbm-bandwidth", "gb200-nvlink-bandwidth", "gb200-nvfp4-sparse", "gb200-nvfp4-dense" ], "compatibility_platform_ids": [ "nvidia-gpu" ] }, { "id": "rubin-gpu", "name": "NVIDIA Rubin GPU", "product_type": "gpu", "architecture": "Rubin", "generation": "Rubin", "family": "NVIDIA Rubin", "market_segment": "Data-center AI training and inference", "availability": "production", "form_factor": "SXM GPU", "claim_ids": [ "rubin-hbm-capacity", "rubin-hbm-bandwidth", "rubin-nvlink-bandwidth", "rubin-nvfp4-inference" ], "compatibility_platform_ids": [ "nvidia-gpu" ] }, { "id": "vera-rubin-nvl72", "name": "NVIDIA Vera Rubin NVL72", "product_type": "system", "architecture": "Vera Rubin platform", "generation": "Rubin", "family": "Vera Rubin", "market_segment": "Rack-scale agentic AI training and inference", "availability": "production", "form_factor": "Liquid-cooled rack-scale system", "system_configuration": "72 Rubin GPUs + 36 Vera CPUs; NVLink 6 rack-scale domain", "notes": "Rack/system record; aggregate values must remain separate from per-GPU specifications.", "claim_ids": [ "rubin-nvl72-gpu-count", "rubin-nvl72-cpu-count" ], "compatibility_platform_ids": [ "nvidia-gpu" ], "related_product_ids": [ "rubin-gpu", "groq3-lpx" ] }, { "id": "groq3-lpu", "name": "NVIDIA Groq 3 LPU", "product_type": "asic", "architecture": "Groq 3 deterministic tensor-streaming LPU", "generation": "Groq 3", "family": "NVIDIA Groq LPU", "market_segment": "Low-latency decode and interactive inference", "availability": "announced", "form_factor": "LPU accelerator", "claim_ids": [ "groq3-sram-capacity", "groq3-sram-bandwidth", "groq3-scaleup-bandwidth" ], "related_product_ids": [ "groq3-lpx" ] }, { "id": "groq3-lpx", "name": "NVIDIA Groq 3 LPX", "product_type": "system", "architecture": "256-LPU rack-scale inference accelerator", "generation": "Groq 3", "family": "NVIDIA Groq LPX", "market_segment": "Rack-scale low-latency agentic inference", "availability": "announced", "form_factor": "Liquid-cooled rack", "system_configuration": "256 Groq 3 LPUs per rack; co-designed to operate alongside Vera Rubin NVL72", "notes": "LPX is a rack-scale LPU system, not a standalone single-chip product.", "claim_ids": [ "lpx-lpu-count", "lpx-sram-capacity", "lpx-sram-bandwidth", "lpx-scaleup-bandwidth", "lpx-fp8-compute" ], "related_product_ids": [ "rubin-gpu", "groq3-lpu", "vera-rubin-nvl72" ] } ], "claims": [ { "id": "b200-memory-capacity", "subject_type": "product", "subject_id": "b200-sxm", "topic": "memory_capacity", "statement": "NVIDIA lists 180 GB of HBM3e memory per B200 SXM GPU.", "value": 180, "unit": "GB HBM3e", "scope": "Per B200 SXM GPU in the HGX B200 8-GPU baseboard.", "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-hgx-b200-docs" ], "last_reviewed": "2026-11-05", "notes": "Vendor specification; not a measured application result.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" } }, { "id": "b200-memory-bandwidth", "subject_type": "product", "subject_id": "b200-sxm", "topic": "memory_bandwidth", "statement": "NVIDIA lists up to 8 TB/s GPU memory bandwidth for B200 SXM.", "value": 8, "unit": "TB/s", "scope": "Per B200 SXM GPU; peak vendor specification.", "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-hgx-b200-docs" ], "last_reviewed": "2026-11-05", "notes": "Peak bandwidth; actual application bandwidth depends on workload and implementation.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" } }, { "id": "b200-nvlink-bandwidth", "subject_type": "product", "subject_id": "b200-sxm", "topic": "interconnect", "statement": "HGX B200 documentation lists 1.8 TB/s GPU-to-GPU bandwidth.", "value": 1.8, "unit": "TB/s", "scope": "GPU-to-GPU bandwidth in the HGX B200 8-GPU baseboard; not external network bandwidth.", "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-hgx-b200-docs" ], "last_reviewed": "2026-11-05", "notes": "System topology figure; retain the HGX B200 configuration boundary.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "interconnect", "directionality": "unspecified", "configuration": "Per GPU NVLink bandwidth in HGX B200 8-GPU baseboard." } }, { "id": "b200-architecture", "topic": "architecture", "statement": "NVIDIA identifies HGX B200 as a Blackwell platform built around B200 GPUs.", "value": "Blackwell", "scope": "Architecture family for the B200 GPU in the HGX B200 platform.", "notes": "Vendor product architecture description.", "subject_type": "product", "subject_id": "b200-sxm", "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-hgx-b200-docs" ], "last_reviewed": "2026-11-05" }, { "id": "gb200-gpu-count", "subject_type": "product", "subject_id": "gb200-nvl72", "topic": "deployment", "statement": "NVIDIA specifies 72 Blackwell GPUs in a GB200 NVL72 rack.", "value": 72, "unit": "GPUs", "scope": "Per GB200 NVL72 rack.", "metric_context": { "metric_type": "specification", "measurement_scope": "rack", "operation": "system_configuration" }, "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-gb200-nvl72-specs" ], "last_reviewed": "2026-11-05" }, { "id": "gb200-hbm-capacity", "subject_type": "product", "subject_id": "gb200-nvl72", "topic": "memory_capacity", "statement": "NVIDIA lists 13.4 TB of HBM3E GPU memory for GB200 NVL72.", "value": 13.4, "unit": "TB HBM3E", "scope": "Aggregate GPU memory across 72 GPUs in one rack.", "metric_context": { "metric_type": "specification", "measurement_scope": "rack", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-gb200-nvl72-specs" ], "last_reviewed": "2026-11-05" }, { "id": "gb200-hbm-bandwidth", "subject_type": "product", "subject_id": "gb200-nvl72", "topic": "memory_bandwidth", "statement": "NVIDIA lists up to 576 TB/s aggregate GPU memory bandwidth for GB200 NVL72.", "value": 576, "unit": "TB/s", "scope": "Aggregate HBM bandwidth across the 72-GPU rack.", "metric_context": { "metric_type": "specification", "measurement_scope": "rack", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-gb200-nvl72-specs" ], "last_reviewed": "2026-11-05" }, { "id": "gb200-nvlink-bandwidth", "subject_type": "product", "subject_id": "gb200-nvl72", "topic": "interconnect", "statement": "NVIDIA lists 130 TB/s NVLink bandwidth for the GB200 NVL72 rack.", "value": 130, "unit": "TB/s", "scope": "NVLink fabric bandwidth for the 72-GPU rack.", "metric_context": { "metric_type": "specification", "measurement_scope": "rack", "operation": "interconnect", "directionality": "unspecified" }, "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-gb200-nvl72-specs" ], "last_reviewed": "2026-11-05" }, { "id": "gb200-nvfp4-sparse", "subject_type": "product", "subject_id": "gb200-nvl72", "topic": "compute", "statement": "NVIDIA lists up to 1,440 PFLOPs NVFP4 Tensor Core performance for GB200 NVL72 with sparsity.", "value": 1440, "unit": "PFLOPs NVFP4", "scope": "Aggregate rack-level Tensor Core peak; sparse specification.", "metric_context": { "metric_type": "theoretical_peak", "measurement_scope": "rack", "operation": "matrix", "precision": "NVFP4", "sparsity": "structured_sparse" }, "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-gb200-nvl72-specs" ], "last_reviewed": "2026-11-05", "notes": "Sparse vendor peak. The corresponding dense figure is half the sparse specification." }, { "id": "gb200-nvfp4-dense", "subject_type": "product", "subject_id": "gb200-nvl72", "topic": "compute", "statement": "The dense NVFP4 Tensor Core peak corresponding to NVIDIA's 1,440 PFLOPs sparse figure is 720 PFLOPs.", "value": 720, "unit": "PFLOPs NVFP4", "scope": "Aggregate rack-level Tensor Core peak; dense specification derived from NVIDIA's published sparse/dense footnote.", "metric_context": { "metric_type": "theoretical_peak", "measurement_scope": "rack", "operation": "matrix", "precision": "NVFP4", "sparsity": "dense" }, "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-gb200-nvl72-specs" ], "last_reviewed": "2026-11-05", "notes": "Derived by applying NVIDIA's explicit footnote that dense performance is one-half of the sparse figure; not a separate measured result." }, { "id": "rubin-hbm-capacity", "subject_type": "product", "subject_id": "rubin-gpu", "topic": "memory_capacity", "statement": "NVIDIA lists up to 288 GB of HBM4 per Rubin GPU.", "value": 288, "unit": "GB HBM4", "scope": "Per Rubin GPU.", "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-rubin-gpu-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" } }, { "id": "rubin-hbm-bandwidth", "subject_type": "product", "subject_id": "rubin-gpu", "topic": "memory_bandwidth", "statement": "NVIDIA lists up to 22 TB/s HBM4 bandwidth per Rubin GPU.", "value": 22, "unit": "TB/s", "scope": "Per Rubin GPU; peak vendor specification.", "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-rubin-gpu-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" } }, { "id": "rubin-nvlink-bandwidth", "subject_type": "product", "subject_id": "rubin-gpu", "topic": "interconnect", "statement": "NVIDIA lists 3.6 TB/s bidirectional NVLink 6 bandwidth per Rubin GPU.", "value": 3.6, "unit": "TB/s", "scope": "Per GPU, NVLink 6 bidirectional bandwidth.", "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-rubin-gpu-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "interconnect", "directionality": "bidirectional" } }, { "id": "rubin-nvfp4-inference", "subject_type": "product", "subject_id": "rubin-gpu", "topic": "compute", "statement": "NVIDIA lists up to 50 PFLOPS NVFP4 inference performance per Rubin GPU.", "value": 50, "unit": "PFLOPS NVFP4", "scope": "Per Rubin GPU; NVIDIA table labels this a sparse inference specification.", "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-rubin-gpu-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "theoretical_peak", "measurement_scope": "chip", "operation": "matrix", "precision": "NVFP4", "sparsity": "unspecified" }, "notes": "Vendor peak; sparse mode is not further normalized." }, { "id": "rubin-nvl72-gpu-count", "subject_type": "product", "subject_id": "vera-rubin-nvl72", "topic": "system_scale", "statement": "NVIDIA Vera Rubin NVL72 integrates 72 Rubin GPUs.", "value": 72, "unit": "GPUs", "scope": "Per Vera Rubin NVL72 rack.", "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-vera-rubin-platform" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "rack", "operation": "system_configuration" } }, { "id": "rubin-nvl72-cpu-count", "subject_type": "product", "subject_id": "vera-rubin-nvl72", "topic": "system_scale", "statement": "NVIDIA Vera Rubin NVL72 integrates 36 Vera CPUs.", "value": 36, "unit": "CPUs", "scope": "Per Vera Rubin NVL72 rack.", "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-vera-rubin-platform" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "rack", "operation": "system_configuration" } }, { "id": "groq3-sram-capacity", "subject_type": "product", "subject_id": "groq3-lpu", "topic": "memory_capacity", "statement": "NVIDIA lists 500 MB SRAM per Groq 3 LPU.", "value": 500, "unit": "MB SRAM", "scope": "Per Groq 3 LPU.", "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-groq3-lpx-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" } }, { "id": "groq3-sram-bandwidth", "subject_type": "product", "subject_id": "groq3-lpu", "topic": "memory_bandwidth", "statement": "NVIDIA lists 150 TB/s SRAM bandwidth per Groq 3 LPU.", "value": 150, "unit": "TB/s", "scope": "Per Groq 3 LPU.", "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-groq3-lpx-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" } }, { "id": "groq3-scaleup-bandwidth", "subject_type": "product", "subject_id": "groq3-lpu", "topic": "interconnect", "statement": "NVIDIA lists 2.5 TB/s scale-up bandwidth per Groq 3 LPU.", "value": 2.5, "unit": "TB/s", "scope": "Per Groq 3 LPU; directionality not specified.", "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-groq3-lpx-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "interconnect", "directionality": "unspecified" } }, { "id": "lpx-lpu-count", "subject_type": "product", "subject_id": "groq3-lpx", "topic": "system_scale", "statement": "Each NVIDIA Groq 3 LPX rack integrates 256 interconnected LPU accelerators.", "value": 256, "unit": "LPUs", "scope": "Per LPX rack.", "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-groq3-lpx-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "rack", "operation": "system_configuration" } }, { "id": "lpx-sram-capacity", "subject_type": "product", "subject_id": "groq3-lpx", "topic": "memory_capacity", "statement": "NVIDIA lists 128 GB total on-chip SRAM per LPX rack.", "value": 128, "unit": "GB SRAM", "scope": "Aggregate across 256 LPUs in one LPX rack.", "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-groq3-lpx-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "rack", "operation": "memory" } }, { "id": "lpx-sram-bandwidth", "subject_type": "product", "subject_id": "groq3-lpx", "topic": "memory_bandwidth", "statement": "NVIDIA lists 40 PB/s aggregate SRAM bandwidth per LPX rack.", "value": 40, "unit": "PB/s", "scope": "Aggregate across one LPX rack.", "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-groq3-lpx-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "rack", "operation": "memory" } }, { "id": "lpx-scaleup-bandwidth", "subject_type": "product", "subject_id": "groq3-lpx", "topic": "interconnect", "statement": "NVIDIA lists 640 TB/s scale-up bandwidth across the LPX rack.", "value": 640, "unit": "TB/s", "scope": "Aggregate LPX rack scale-up fabric.", "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-groq3-lpx-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "rack", "operation": "interconnect", "directionality": "unspecified" } }, { "id": "lpx-fp8-compute", "subject_type": "product", "subject_id": "groq3-lpx", "topic": "compute", "statement": "NVIDIA lists 315 PFLOPS FP8 inference compute per LPX rack.", "value": 315, "unit": "PFLOPS FP8", "scope": "Aggregate per LPX rack.", "claim_status": "vendor_reported", "evidence_ids": [ "nvidia-groq3-lpx-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "theoretical_peak", "measurement_scope": "rack", "operation": "matrix", "precision": "FP8", "sparsity": "unspecified" } } ], "evidence": [ { "id": "nvidia-hgx-b200-docs", "title": "NVIDIA HGX AI Factory — B200 component specifications", "url": "https://docs.nvidia.com/enterprise-reference-architectures/hgx-ai-factory-h100-h200-b200/latest/components.html", "publisher": "NVIDIA", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2026-08-31", "checked_at": "2026-11-05", "review_status": "reviewed", "notes": "Official vendor documentation checked on 2026-11-05. These are vendor-published specifications, not independent benchmark measurements. The documentation page states it was last updated on 2026-08-31." }, { "id": "nvidia-gb200-nvl72-specs", "title": "NVIDIA GB200 NVL72 official specifications", "url": "https://www.nvidia.com/en-us/data-center/gb200-nvl72/", "publisher": "NVIDIA", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-05", "review_status": "reviewed", "notes": "Official NVIDIA product page. Rack-level values describe the complete 72-GPU GB200 NVL72 system; tensor performance figures are published with sparsity unless stated otherwise." }, { "id": "nvidia-rubin-gpu-specs", "title": "Inside the NVIDIA Rubin Platform — Rubin GPU specifications", "url": "https://developer.nvidia.com/blog/inside-the-nvidia-rubin-platform-six-new-chips-one-ai-supercomputer/", "publisher": "NVIDIA", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2026-01-05", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official NVIDIA technical blog. Per-GPU HBM4, memory bandwidth and NVLink figures; compute figures are precision/mode-specific vendor peaks." }, { "id": "nvidia-groq3-lpx-specs", "title": "NVIDIA Groq 3 LPX — product specifications", "url": "https://www.nvidia.com/en-us/data-center/lpx/", "publisher": "NVIDIA", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official NVIDIA product page for Groq 3 LPU and LPX rack. Per-LPU and rack-level quantities are kept distinct." }, { "id": "nvidia-vera-rubin-platform", "title": "NVIDIA Vera Rubin Platform", "url": "https://www.nvidia.com/en-us/data-center/technologies/rubin/", "publisher": "NVIDIA", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official NVIDIA platform page. NVL72 configuration is a rack-level system claim." } ], "references": [ { "id": "ref-nvidia-1", "label": "Vera Rubin opens agentic AI frontier", "url": "https://investor.nvidia.com/news/press-release-details/2026/NVIDIA-Vera-Rubin-Opens-Agentic-AI-Frontier/default.aspx", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-nvidia-2", "label": "Vera Rubin POD / rack-scale systems", "url": "https://developer.nvidia.com/blog/nvidia-vera-rubin-pod-seven-chips-five-rack-scale-systems-one-ai-supercomputer/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-nvidia-3", "label": "Hopper in-depth", "url": "https://developer.nvidia.com/blog/nvidia-hopper-architecture-in-depth", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-nvidia-4", "label": "Hopper", "url": "https://www.nvidia.com/en-us/data-center/technologies/hopper-architecture/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-nvidia-5", "label": "Blackwell", "url": "https://www.nvidia.com/en-us/data-center/technologies/blackwell-architecture/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-nvidia-rubin-2026", "label": "Rubin GPU and Vera Rubin platform", "url": "https://developer.nvidia.com/blog/inside-the-nvidia-rubin-platform-six-new-chips-one-ai-supercomputer/", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": "2026-01-05", "checked_at": "2026-11-06", "notes": "Reviewed against NVIDIA's published GPU and system specifications." }, { "id": "ref-nvidia-groq3-lpx", "label": "Groq 3 LPU / LPX product page", "url": "https://www.nvidia.com/en-us/data-center/lpx/", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": null, "checked_at": "2026-11-06", "notes": "Reviewed against NVIDIA product page; per-LPU and per-rack boundaries retained." } ] }, { "id": "habana", "display_name": "Intel / Habana Gaudi", "category": "IC Vendors", "directory_anchor": "Habana", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Intel_logo.png", "summary": "Intel acquired Habana Labs in December 2019. Habana's accelerator architecture and software lineage continue as Intel Gaudi; this profile covers the current Intel Gaudi products and should not be counted as a separate independent company.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [ { "id": "gaudi2", "name": "Intel Gaudi 2", "product_type": "asic", "architecture": "Habana Gaudi2", "generation": "Gaudi 2", "family": "Intel Gaudi", "market_segment": "Data-center AI training and inference", "availability": "shipping", "form_factor": "OAM accelerator module", "claim_ids": [ "gaudi2-memory-capacity", "gaudi2-memory-bandwidth", "gaudi2-network-bandwidth" ], "compatibility_platform_ids": [ "intel-gaudi" ] }, { "id": "gaudi3", "name": "Intel Gaudi 3", "product_type": "asic", "architecture": "Habana Gaudi3", "generation": "Gaudi 3", "family": "Intel Gaudi", "process_node": "TSMC 5nm", "market_segment": "Enterprise generative AI training and inference", "availability": "shipping", "form_factor": "OAM accelerator / PCIe card", "notes": "White-paper figures refer to the Gaudi 3 accelerator architecture; distinguish OAM and PCIe product configurations where board power or I/O differs.", "claim_ids": [ "gaudi3-memory-capacity", "gaudi3-memory-bandwidth", "gaudi3-fp8-peak", "gaudi3-rdma-ports" ], "compatibility_platform_ids": [ "intel-gaudi" ] }, { "id": "intel-gpu-d270", "name": "Intel GPU D270 (Crescent Island)", "product_type": "gpu", "architecture": "Intel Xe3P", "generation": "Intel GPU D-series", "family": "Intel Data Center GPU D-series", "market_segment": "Memory-rich data-center AI inference", "availability": "announced", "form_factor": "350 W air-cooled PCIe 5.0 accelerator card", "claim_ids": [ "d270-memory-capacity", "d270-memory-bandwidth", "d270-power", "d270-compute" ] } ], "claims": [ { "id": "gaudi2-memory-capacity", "subject_type": "product", "subject_id": "gaudi2", "topic": "memory_capacity", "statement": "Intel specifies 96 GB of HBM2E memory per Gaudi2 accelerator.", "value": 96, "unit": "GB HBM2E", "scope": "Per Gaudi2 accelerator.", "metric_context": { "metric_type": "specification", "measurement_scope": "module", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "intel-gaudi2-whitepaper" ], "last_reviewed": "2026-11-05" }, { "id": "gaudi2-memory-bandwidth", "subject_type": "product", "subject_id": "gaudi2", "topic": "memory_bandwidth", "statement": "Intel specifies 2.45 TB/s HBM bandwidth for Gaudi2.", "value": 2.45, "unit": "TB/s", "scope": "Per Gaudi2 accelerator.", "metric_context": { "metric_type": "specification", "measurement_scope": "module", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "intel-gaudi2-whitepaper" ], "last_reviewed": "2026-11-05" }, { "id": "gaudi2-network-bandwidth", "subject_type": "product", "subject_id": "gaudi2", "topic": "interconnect", "statement": "Intel specifies 2.4 Tb/s native networking bandwidth from 24 integrated 100 Gb/s RoCE NICs.", "value": 2.4, "unit": "Tb/s", "scope": "Aggregate integrated NIC bandwidth per Gaudi2 accelerator.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "interconnect", "directionality": "aggregate", "configuration": "24 x 100 Gb/s RoCE v2 NICs" }, "claim_status": "vendor_reported", "evidence_ids": [ "intel-gaudi2-whitepaper" ], "last_reviewed": "2026-11-05" }, { "id": "gaudi3-memory-capacity", "subject_type": "product", "subject_id": "gaudi3", "topic": "memory_capacity", "statement": "Intel specifies 128 GB of HBM2E memory for Gaudi3.", "value": 128, "unit": "GB HBM2E", "scope": "Per Gaudi3 accelerator.", "metric_context": { "metric_type": "specification", "measurement_scope": "module", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "intel-gaudi3-whitepaper" ], "last_reviewed": "2026-11-05" }, { "id": "gaudi3-memory-bandwidth", "subject_type": "product", "subject_id": "gaudi3", "topic": "memory_bandwidth", "statement": "Intel specifies 3.7 TB/s HBM bandwidth for Gaudi3.", "value": 3.7, "unit": "TB/s", "scope": "Per Gaudi3 accelerator.", "metric_context": { "metric_type": "specification", "measurement_scope": "module", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "intel-gaudi3-whitepaper" ], "last_reviewed": "2026-11-05" }, { "id": "gaudi3-fp8-peak", "subject_type": "product", "subject_id": "gaudi3", "topic": "compute", "statement": "Intel specifies 1.8 PFLOPs peak FP8 compute for Gaudi3.", "value": 1.8, "unit": "PFLOPs FP8", "scope": "Per Gaudi3 accelerator; vendor peak specification.", "metric_context": { "metric_type": "theoretical_peak", "measurement_scope": "module", "operation": "matrix", "precision": "FP8", "sparsity": "dense" }, "claim_status": "vendor_reported", "evidence_ids": [ "intel-gaudi3-whitepaper" ], "last_reviewed": "2026-11-05" }, { "id": "gaudi3-rdma-ports", "subject_type": "product", "subject_id": "gaudi3", "topic": "interconnect", "statement": "Intel specifies 24 integrated 200 Gb/s RDMA NIC ports on Gaudi3.", "value": 24, "unit": "ports x 200 Gb/s", "scope": "Integrated NIC port count per Gaudi3 accelerator.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "interconnect", "directionality": "aggregate" }, "claim_status": "vendor_reported", "evidence_ids": [ "intel-gaudi3-whitepaper" ], "last_reviewed": "2026-11-05" }, { "id": "d270-memory-capacity", "subject_type": "product", "subject_id": "intel-gpu-d270", "topic": "memory_capacity", "statement": "Intel lists up to 480 GB LPDDR5X memory per D-series card design.", "value": 480, "unit": "GB LPDDR5X", "scope": "Maximum capacity of D-series partner card designs; Intel-branded card configurations may differ.", "claim_status": "vendor_reported", "evidence_ids": [ "intel-d270-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "module", "operation": "memory" } }, { "id": "d270-memory-bandwidth", "subject_type": "product", "subject_id": "intel-gpu-d270", "topic": "memory_bandwidth", "statement": "Intel lists up to 1.5 TB/s memory bandwidth for Crescent Island.", "value": 1.5, "unit": "TB/s", "scope": "Accelerator memory bandwidth; vendor specification.", "claim_status": "vendor_reported", "evidence_ids": [ "intel-d270-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "module", "operation": "memory" } }, { "id": "d270-power", "subject_type": "product", "subject_id": "intel-gpu-d270", "topic": "power", "statement": "Intel lists a 350 W power envelope for GPU D270.", "value": 350, "unit": "W", "scope": "Per D270 accelerator card.", "claim_status": "vendor_reported", "evidence_ids": [ "intel-d270-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "module", "operation": "power" } }, { "id": "d270-compute", "subject_type": "product", "subject_id": "intel-gpu-d270", "topic": "compute", "statement": "Intel lists up to 1.3 PFLOPS FP8 compute for Crescent Island.", "value": 1.3, "unit": "PFLOPS FP8", "scope": "Peak vendor specification; confirm exact board SKU and precision configuration before comparison.", "claim_status": "vendor_reported", "evidence_ids": [ "intel-d270-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "theoretical_peak", "measurement_scope": "module", "operation": "matrix", "precision": "FP8", "sparsity": "unspecified" } } ], "evidence": [ { "id": "intel-gaudi2-whitepaper", "title": "Intel Gaudi2 AI Accelerators White Paper", "url": "https://cdrdv2-public.intel.com/839363/Intel-Gaudi2-AI-Accelerators-whitepaper.pdf", "publisher": "Intel", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-05", "review_status": "reviewed", "notes": "Official Intel/Habana white paper. Memory and networking figures are per accelerator; 2.4 Tb/s is aggregate native networking capacity from 24 x 100 Gb/s RoCE NICs." }, { "id": "intel-gaudi3-whitepaper", "title": "Intel Gaudi 3 AI Accelerator White Paper", "url": "https://cdrdv2-public.intel.com/817486/gaudi-3-ai-accelerator-white-paper.pdf", "publisher": "Intel", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-05", "review_status": "reviewed", "notes": "Official Intel white paper. Describes Gaudi 3's two compute dies, 128 GB HBM2e, 3.7 TB/s bandwidth and 1.8 PFLOPs FP8/BF16 peak compute." }, { "id": "intel-d270-2026", "title": "Intel GPU D-series / Crescent Island product and architecture information", "url": "https://www.intel.com/content/www/us/en/newsroom/news/artificial-intelligence/intel-accelerates-open-infrastructure-agentic-ai-era.html", "publisher": "Intel", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official Intel newsroom source. The 480 GB figure is a maximum across partner card designs; the Intel-branded card may carry less memory." }, { "id": "intel-d270-product-page", "title": "Intel GPU D270 product page", "url": "https://www.intel.com/content/www/us/en/products/details/discrete-gpus/data-center-gpu/d-series.html", "publisher": "Intel", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official Intel product page identifies D270, 350 W air cooling, PCIe 5.0, and inference-focused workload positioning." }, { "id": "intel-habana-acquisition", "title": "Intel acquires artificial intelligence chipmaker Habana Labs", "url": "https://download.intel.com/newsroom/2021/archive/2019-12-16-news-releases-intel-ai-acquisition.pdf", "publisher": "Intel", "source_type": "company_primary", "independence": "vendor", "published_at": "2019-12-16", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Intel's official release confirms the acquisition of Habana Labs in December 2019. The current product lineage is Intel Gaudi; Habana is not an independent vendor." } ], "references": [ { "id": "ref-habana-1", "label": "Gaudi 3 on IBM Cloud", "url": "https://newsroom.intel.com/artificial-intelligence/ibm-cloud-first-service-provider-deploy-intel-gaudi-3", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-habana-2", "label": "Dell AI Factory with Gaudi 3", "url": "https://newsroom.intel.com/artificial-intelligence/intel-gaudi-3-expands-availability-drive-ai-innovation-scale", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-intel-d270", "label": "Intel GPU D270 / Crescent Island", "url": "https://www.intel.com/content/www/us/en/products/details/discrete-gpus/data-center-gpu/d-series.html", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": null, "checked_at": "2026-11-06", "notes": "Reviewed against official Intel product page; memory maximum and card variants require SKU-level qualification." }, { "id": "ref-habana-acquisition", "label": "Intel acquisition of Habana Labs", "url": "https://download.intel.com/newsroom/2021/archive/2019-12-16-news-releases-intel-ai-acquisition.pdf", "source_type": "company_primary", "review_status": "reviewed", "published_at": "2019-12-16", "checked_at": "2026-11-06", "notes": "Intel's official release confirms the acquisition of Habana Labs in December 2019. The current product lineage is Intel Gaudi; Habana is not an independent vendor." } ], "corporate_status": { "ownership_status": "integrated_business_unit", "operating_status": "active", "parent_company": "Intel", "effective_date": "2019-12-16", "transaction_type": "acquisition", "notes": "Habana Labs is an Intel business/product lineage. Gaudi accelerators are marketed as Intel products.", "evidence_ids": [ "intel-habana-acquisition" ] } }, { "id": "amd", "display_name": "AMD — Instinct AI GPUs", "category": "IC Vendors", "directory_anchor": "AMD", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/AMD_logo.png", "summary": "AMD’s datacenter AI story runs through the Instinct line on CDNA architecture (distinct from RDNA gaming GPUs), with ROCm as the software stack. MI100/MI200 established HBM-heavy training SKUs; MI300A/X (CDNA 3, 2023) brought chiplet APU/GPU designs into large LLM clusters. MI350 (CDNA 4, 2025) pushes HBM3E capacity and low-precision datatypes; MI400 / Helios rack systems headline the 2026 roadmap alongside deep hyperscaler partnerships.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [ { "id": "mi355x", "name": "AMD Instinct MI355X", "product_type": "gpu", "architecture": "CDNA 4", "generation": "Instinct MI350 Series", "process_node": "TSMC 3nm | 6nm FinFET", "market_segment": "Data-center AI training and inference", "availability": "shipping", "claim_ids": [ "mi355x-architecture", "mi355x-memory-capacity", "mi355x-memory-bandwidth", "mi355x-mxfp4-peak", "mi355x-tbp", "mi355x-process-node" ], "compatibility_platform_ids": [ "amd-gpu" ] }, { "id": "mi350x", "name": "AMD Instinct MI350X", "product_type": "gpu", "architecture": "CDNA 4", "generation": "Instinct MI350 Series", "family": "AMD Instinct MI350", "process_node": "TSMC 3nm | 6nm FinFET", "market_segment": "Data-center AI training and inference", "availability": "shipping", "form_factor": "OAM accelerator module", "notes": "Per-GPU OAM product record; keep separate from the 8-GPU UBB platform.", "claim_ids": [ "mi350x-memory-capacity", "mi350x-memory-bandwidth", "mi350x-mxfp4-peak", "mi350x-fp8-peak" ], "compatibility_platform_ids": [ "amd-gpu" ] }, { "id": "mi455x", "name": "AMD Instinct MI455X", "product_type": "gpu", "architecture": "5th Gen CDNA 5", "generation": "Instinct MI400 Series", "family": "AMD Instinct MI400", "process_node": "TSMC 2nm | 3nm FinFET", "market_segment": "Frontier AI training and inference", "availability": "announced", "form_factor": "Enhanced Accelerator Module (EAM)", "claim_ids": [ "mi455x-hbm-capacity", "mi455x-hbm-bandwidth", "mi455x-mxfp4-compute", "mi455x-ualoe-bandwidth" ], "compatibility_platform_ids": [ "amd-gpu" ], "related_product_ids": [ "helios-rack" ] }, { "id": "helios-rack", "name": "AMD Helios Rackscale Solution", "product_type": "system", "architecture": "AMD Helios open rack-scale AI platform", "generation": "MI400 / Helios", "family": "AMD Helios", "market_segment": "Rack-scale frontier AI training and inference", "availability": "announced", "form_factor": "Open Rack Wide (ORW) liquid-cooled rack reference design", "system_configuration": "72 MI455X GPUs with AMD EPYC Venice CPUs and Pensando networking", "notes": "AMD describes Helios as a rack-scale reference design for OEM/ODM partners, not a standalone chip.", "claim_ids": [ "helios-gpu-count", "helios-hbm-capacity", "helios-hbm-bandwidth" ], "compatibility_platform_ids": [ "amd-gpu" ], "related_product_ids": [ "mi455x" ] } ], "claims": [ { "id": "mi355x-architecture", "subject_type": "product", "subject_id": "mi355x", "topic": "architecture", "statement": "AMD identifies MI355X as based on its 4th-generation CDNA architecture.", "value": "CDNA 4", "scope": "GPU architecture.", "claim_status": "vendor_reported", "evidence_ids": [ "amd-mi355x-product-page" ], "last_reviewed": "2026-11-05", "notes": "Vendor product specification." }, { "id": "mi355x-memory-capacity", "subject_type": "product", "subject_id": "mi355x", "topic": "memory_capacity", "statement": "AMD lists 288 GB of HBM3E memory for MI355X.", "value": 288, "unit": "GB HBM3E", "scope": "Per MI355X GPU.", "claim_status": "vendor_reported", "evidence_ids": [ "amd-mi355x-product-page" ], "last_reviewed": "2026-11-05", "notes": "Vendor product specification.", "metric_context": { "metric_type": "specification", "measurement_scope": "module", "operation": "memory" } }, { "id": "mi355x-memory-bandwidth", "subject_type": "product", "subject_id": "mi355x", "topic": "memory_bandwidth", "statement": "AMD lists peak memory bandwidth of 8 TB/s for MI355X.", "value": 8, "unit": "TB/s", "scope": "Per MI355X GPU; peak vendor specification.", "claim_status": "vendor_reported", "evidence_ids": [ "amd-mi355x-product-page" ], "last_reviewed": "2026-11-05", "notes": "Peak bandwidth; not an application measurement.", "metric_context": { "metric_type": "specification", "measurement_scope": "module", "operation": "memory" } }, { "id": "mi355x-mxfp4-peak", "subject_type": "product", "subject_id": "mi355x", "topic": "compute", "statement": "AMD lists 10.1 PFLOPs peak MXFP4 matrix performance for MI355X.", "value": 10.1, "unit": "PFLOPs", "scope": "Per MI355X GPU; peak MXFP4 matrix specification.", "claim_status": "vendor_reported", "evidence_ids": [ "amd-mi355x-product-page" ], "last_reviewed": "2026-11-05", "notes": "Vendor theoretical peak; keep precision and matrix-operation context when comparing.", "metric_context": { "metric_type": "theoretical_peak", "measurement_scope": "module", "operation": "matrix", "precision": "MXFP4", "sparsity": "dense" } }, { "id": "mi355x-tbp", "subject_type": "product", "subject_id": "mi355x", "topic": "power", "statement": "AMD lists typical board power (TBP) of 1,400 W for MI355X.", "value": 1400, "unit": "W TBP", "scope": "MI355X OAM module; vendor-listed TBP.", "claim_status": "vendor_reported", "evidence_ids": [ "amd-mi355x-product-page" ], "last_reviewed": "2026-11-05", "notes": "TBP is not a measured wall-power value for a full server.", "metric_context": { "metric_type": "specification", "measurement_scope": "module", "operation": "power" } }, { "id": "mi355x-process-node", "topic": "process_node", "statement": "AMD lists TSMC 3nm and 6nm FinFET lithography for MI355X.", "value": "TSMC 3nm | 6nm FinFET", "scope": "Process technologies listed in AMD's MI355X product specifications.", "notes": "Vendor-published lithography information; the page does not assign each process node to a specific die in this record.", "subject_type": "product", "subject_id": "mi355x", "claim_status": "vendor_reported", "evidence_ids": [ "amd-mi355x-product-page" ], "last_reviewed": "2026-11-05" }, { "id": "mi350x-memory-capacity", "subject_type": "product", "subject_id": "mi350x", "topic": "memory_capacity", "statement": "AMD lists 288 GB of HBM3E memory per MI350X GPU.", "value": 288, "unit": "GB HBM3E", "scope": "Per MI350X GPU.", "metric_context": { "metric_type": "specification", "measurement_scope": "module", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "amd-mi350-series-specs" ], "last_reviewed": "2026-11-05" }, { "id": "mi350x-memory-bandwidth", "subject_type": "product", "subject_id": "mi350x", "topic": "memory_bandwidth", "statement": "AMD lists 8 TB/s peak memory bandwidth per MI350X GPU.", "value": 8, "unit": "TB/s", "scope": "Per MI350X GPU; peak theoretical specification.", "metric_context": { "metric_type": "specification", "measurement_scope": "module", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "amd-mi350-series-specs" ], "last_reviewed": "2026-11-05" }, { "id": "mi350x-mxfp4-peak", "subject_type": "product", "subject_id": "mi350x", "topic": "compute", "statement": "AMD lists 9.2 PFLOPs peak theoretical MXFP4 matrix performance for MI350X.", "value": 9.2, "unit": "PFLOPs MXFP4", "scope": "Per MI350X GPU; dense matrix performance.", "metric_context": { "metric_type": "theoretical_peak", "measurement_scope": "module", "operation": "matrix", "precision": "MXFP4", "sparsity": "dense" }, "claim_status": "vendor_reported", "evidence_ids": [ "amd-mi350-series-specs" ], "last_reviewed": "2026-11-05" }, { "id": "mi350x-fp8-peak", "subject_type": "product", "subject_id": "mi350x", "topic": "compute", "statement": "AMD lists 4.6 PFLOPs peak theoretical MXFP8/OCP-FP8 matrix performance for MI350X.", "value": 4.6, "unit": "PFLOPs MXFP8/OCP-FP8", "scope": "Per MI350X GPU; dense matrix performance as presented in AMD's MI350 Series table.", "metric_context": { "metric_type": "theoretical_peak", "measurement_scope": "module", "operation": "matrix", "precision": "MXFP8", "sparsity": "dense" }, "claim_status": "vendor_reported", "evidence_ids": [ "amd-mi350-series-specs" ], "last_reviewed": "2026-11-05", "notes": "AMD presents MXFP8/OCP-FP8 together in this table; retain the combined source wording in the unit and statement." }, { "id": "mi455x-hbm-capacity", "subject_type": "product", "subject_id": "mi455x", "topic": "memory_capacity", "statement": "AMD lists 432 GB HBM4 per MI455X GPU.", "value": 432, "unit": "GB HBM4", "scope": "Per MI455X GPU.", "claim_status": "vendor_reported", "evidence_ids": [ "amd-mi455x-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" } }, { "id": "mi455x-hbm-bandwidth", "subject_type": "product", "subject_id": "mi455x", "topic": "memory_bandwidth", "statement": "AMD lists up to 23.3 TB/s peak memory bandwidth per MI455X GPU.", "value": 23.3, "unit": "TB/s", "scope": "Per MI455X GPU.", "claim_status": "vendor_reported", "evidence_ids": [ "amd-mi455x-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" } }, { "id": "mi455x-mxfp4-compute", "subject_type": "product", "subject_id": "mi455x", "topic": "compute", "statement": "AMD lists 40.3 PFLOPS peak OCP MXFP4 performance per MI455X GPU.", "value": 40.3, "unit": "PFLOPS MXFP4", "scope": "Per MI455X GPU; peak vendor specification.", "claim_status": "vendor_reported", "evidence_ids": [ "amd-mi455x-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "theoretical_peak", "measurement_scope": "chip", "operation": "matrix", "precision": "MXFP4", "sparsity": "unspecified" } }, { "id": "mi455x-ualoe-bandwidth", "subject_type": "product", "subject_id": "mi455x", "topic": "interconnect", "statement": "AMD lists 3.6 TB/s peak bidirectional UALoE scale-up bandwidth per MI455X board.", "value": 3.6, "unit": "TB/s", "scope": "Per MI455X accelerator module; UALoE bidirectional scale-up.", "claim_status": "vendor_reported", "evidence_ids": [ "amd-mi455x-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "module", "operation": "interconnect", "directionality": "bidirectional" } }, { "id": "helios-gpu-count", "subject_type": "product", "subject_id": "helios-rack", "topic": "system_scale", "statement": "AMD Helios connects 72 MI455X GPUs in one rack-scale solution.", "value": 72, "unit": "GPUs", "scope": "Per Helios rack.", "claim_status": "vendor_reported", "evidence_ids": [ "amd-helios-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "rack", "operation": "system_configuration" } }, { "id": "helios-hbm-capacity", "subject_type": "product", "subject_id": "helios-rack", "topic": "memory_capacity", "statement": "AMD lists 31 TB total HBM4 capacity per Helios rack.", "value": 31, "unit": "TB HBM4", "scope": "Aggregate across 72 GPUs in one Helios rack.", "claim_status": "vendor_reported", "evidence_ids": [ "amd-helios-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "rack", "operation": "memory" } }, { "id": "helios-hbm-bandwidth", "subject_type": "product", "subject_id": "helios-rack", "topic": "memory_bandwidth", "statement": "AMD lists up to 1.67 PB/s aggregate HBM bandwidth per Helios rack.", "value": 1.67, "unit": "PB/s", "scope": "Aggregate theoretical memory bandwidth per Helios rack.", "claim_status": "vendor_reported", "evidence_ids": [ "amd-helios-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "rack", "operation": "memory" } } ], "evidence": [ { "id": "amd-mi355x-product-page", "title": "AMD Instinct MI355X product specifications", "url": "https://www.amd.com/en/products/accelerators/instinct/mi350/mi355x.html", "publisher": "AMD", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-05", "review_status": "reviewed", "notes": "Official vendor documentation checked on 2026-11-05. These are vendor-published specifications, not independent benchmark measurements." }, { "id": "amd-mi350-series-specs", "title": "AMD Instinct MI350 Series specifications", "url": "https://www.amd.com/en/blogs/2025/amd-instinct-mi350-series-and-beyond-accelerating-the-future-of-ai-and-hpc.html", "publisher": "AMD", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2025-06-12", "checked_at": "2026-11-05", "review_status": "reviewed", "notes": "Official AMD product-family article. The table labels performance values as peak theoretical; dense matrix values are kept separate from sparse figures." }, { "id": "amd-mi455x-2026", "title": "AMD Instinct MI455X GPU specifications", "url": "https://www.amd.com/en/products/accelerators/instinct/mi400/mi455x.html", "publisher": "AMD", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official AMD product specification page. Memory, compute and board interconnect values are vendor specifications." }, { "id": "amd-helios-2026", "title": "AMD launches Helios rackscale AI infrastructure", "url": "https://www.amd.com/en/blogs/2026/amd-launches-helios-the-highest-performing-rackscale-ai-infrastructure-solution.html", "publisher": "AMD", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2026-07-23", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official AMD announcement. Helios is a reference design; system totals must not be compared with per-GPU values." } ], "references": [ { "id": "ref-amd-1", "label": "AMD–Meta 6GW Instinct partnership", "url": "https://www.amd.com/en/newsroom/press-releases/2026-2-24-amd-and-meta-announce-expanded-strategic-partnersh.html", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-amd-2", "label": "Helios / MI400 series on track", "url": "https://www.nextplatform.com/compute/2026/02/23/amd-says-helios-racks-and-mi400-series-gpus-on-track-for-2h-2026/4092199", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-amd-mi455x-2026", "label": "MI455X GPU specification", "url": "https://www.amd.com/en/products/accelerators/instinct/mi400/mi455x.html", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": null, "checked_at": "2026-11-06", "notes": "Reviewed against official product specifications." }, { "id": "ref-amd-helios-2026", "label": "Helios rack-scale reference design", "url": "https://www.amd.com/en/blogs/2026/amd-launches-helios-the-highest-performing-rackscale-ai-infrastructure-solution.html", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": "2026-07-23", "checked_at": "2026-11-06", "notes": "Reviewed; Helios is explicitly labeled as a partner reference design." } ] }, { "id": "qualcomm", "display_name": "Qualcomm — Hexagon NPU & Dragonfly data-center AI", "category": "IC Vendors", "directory_anchor": "Qualcomm", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Qualcomm_logo.png", "summary": "Qualcomm’s AI silicon now spans mobile Hexagon NPUs in Snapdragon SoCs and a full data-center Dragonfly portfolio for agentic inference. Hexagon evolved from DSP blocks into fused scalar/vector/tensor NPUs for on-device GenAI; Cloud AI 100 was an earlier inference SKU. In Oct 2025 Qualcomm launched rack-scale Dragonfly AI200/AI250 inference accelerators, then at Investor Day Jun 2026 added AI300 with High Bandwidth Compute (HBC), the Dragonfly C1000 server CPU (Meta multi-generation agreement), and a multi-year data-center revenue push.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-qualcomm-1", "label": "Dragonfly AI300 / data-center roadmap", "url": "https://sg.finance.yahoo.com/news/qualcomm-unveils-comprehensive-data-center-193000894.html", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-qualcomm-2", "label": "Dragonfly AI200 / AI250 launch", "url": "https://www.datacenterdynamics.com/en/news/qualcomm-launches-ai200-and-ai250-chip-offering-targeting-inferencing-workloads-at-rack-scale/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "samsung", "display_name": "Samsung — Exynos NPU", "category": "IC Vendors", "directory_anchor": "Samsung", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Samsung_logo.png", "summary": "Samsung integrates NPUs into Exynos mobile SoCs and builds HBM that underpins datacenter AI GPUs. Exynos NPUs scaled with each flagship for vision and on-device GenAI; Exynos 2500 (3nm GAA) was followed by Exynos 2600 — Samsung’s first 2nm GAA mobile SoC — powering Galaxy S26 with substantially higher generative-AI NPU performance and AI graphics features (ENSS).", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-samsung-1", "label": "Exynos 2600", "url": "https://semiconductor.samsung.com/processor/mobile-processor/exynos-2600/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-samsung-2", "label": "ENSS AI graphics on Exynos 2600", "url": "https://www.asiae.co.kr/en/article/2026042810393630443", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "media-tek", "display_name": "MediaTek — Dimensity NPU", "category": "IC Vendors", "directory_anchor": "MediaTek", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/MediaTek_logo.png", "summary": "MediaTek’s Dimensity flagship line pairs Arm CPUs with successive in-house NPUs for Android on-device AI. The NPU roadmap (through 8th-gen NPU 890 on Dimensity 9400) emphasizes generative and agentic workloads—LoRA adaptation, diffusion video, and MoE LLMs—alongside the Dimensity Agentic AI Engine software path.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-media-tek-1", "label": "Dimensity 9500 — NPU 990", "url": "https://www.mediatek.com/press-room/mediatek-dimensity-9500-unleashes-best-in-class-performance-ai-experiences-and-power-efficiency-for-the-next-generation-of-mobile-devices", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "marvell", "display_name": "Marvell — custom AI ASICs & DPUs", "category": "IC Vendors", "directory_anchor": "Marvell", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Marvell_logo.png", "summary": "Marvell's AI silicon opportunity is primarily customer-specific custom ASICs, custom HBM and scale-up connectivity. The registry intentionally records a platform rather than inventing merchant XPU SKUs.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [ { "id": "marvell-custom-xpu-platform", "name": "Marvell Custom XPU / HBM Compute Architecture", "product_type": "asic", "architecture": "Custom compute die with tailored HBM base-die interfaces, die-to-die links and advanced packaging", "generation": "Custom XPU platform", "family": "Marvell Custom Silicon", "market_segment": "Hyperscale AI accelerator ASICs", "availability": "announced", "form_factor": "Customer-specific multi-die package", "claim_ids": [ "marvell-custom-hbm-area", "marvell-custom-hbm-capacity", "marvell-custom-hbm-power", "marvell-nvlink-fusion" ], "availability_history": [ { "status": "announced", "effective_at": "2024-12-10", "evidence_id": "marvell-custom-hbm", "notes": "Custom HBM compute architecture announced." }, { "status": "announced", "effective_at": "2026-03-31", "evidence_id": "marvell-nvlink-fusion", "notes": "Marvell announced NVLink Fusion collaboration for custom XPUs." } ] } ], "claims": [ { "id": "marvell-custom-hbm-area", "subject_type": "product", "subject_id": "marvell-custom-xpu-platform", "topic": "architecture", "statement": "Marvell says its custom HBM architecture can free up to 25% more compute-die area for compute.", "scope": "Vendor-stated design benefit versus conventional HBM interface; not a measured customer-product benchmark.", "claim_status": "vendor_reported", "evidence_ids": [ "marvell-custom-hbm" ], "last_reviewed": "2026-11-06" }, { "id": "marvell-custom-hbm-capacity", "subject_type": "product", "subject_id": "marvell-custom-xpu-platform", "topic": "memory_capacity", "statement": "Marvell says the architecture can enable up to 33% greater memory capacity.", "scope": "Vendor-stated architecture-level potential; not a universal shipped-product specification.", "claim_status": "vendor_reported", "evidence_ids": [ "marvell-custom-hbm" ], "last_reviewed": "2026-11-06" }, { "id": "marvell-custom-hbm-power", "subject_type": "product", "subject_id": "marvell-custom-xpu-platform", "topic": "power", "statement": "Marvell says the custom memory interface can reduce memory-interface power by up to 70%.", "scope": "Vendor-stated interface-level potential; not whole-chip or system power.", "claim_status": "vendor_reported", "evidence_ids": [ "marvell-custom-hbm" ], "last_reviewed": "2026-11-06" }, { "id": "marvell-nvlink-fusion", "subject_type": "product", "subject_id": "marvell-custom-xpu-platform", "topic": "interconnect", "statement": "Marvell will provide custom XPUs and NVLink Fusion-compatible scale-up networking.", "scope": "Partnership-level capability; no public named accelerator SKU or chip-level throughput disclosed.", "claim_status": "vendor_reported", "evidence_ids": [ "marvell-nvlink-fusion" ], "last_reviewed": "2026-11-06" } ], "evidence": [ { "id": "marvell-custom-hbm", "title": "Custom HBM Compute Architecture", "url": "https://www.marvell.com/products/custom-asic/custom-hbm-compute-architecture.html", "publisher": "Marvell", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official architecture page; percentages are vendor-stated design potential and must not be interpreted as measured product performance." }, { "id": "marvell-nvlink-fusion", "title": "NVIDIA AI Ecosystem Expands as Marvell Joins Forces Through NVLink Fusion", "url": "https://www.marvell.com/company/newsroom/nvidia-ai-ecosystem-expands-marvell-joins-forces-through-nvlink-fusion.html", "publisher": "Marvell", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2026-03-31", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official announcement dated 2026-03-31. Marvell provides custom XPUs and compatible scale-up networking; no XPU SKU specifications published." } ], "references": [ { "id": "ref-marvell-1", "label": "Expanding custom silicon opportunity", "url": "https://www.marvell.com/blogs/inside-marvell-expanding-custom-silicon-opportunity.html", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-marvell-2", "label": "Hyperscaler AI ASIC programs", "url": "https://www.marvell.com/products/data-processing-units.html", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-marvell-custom-hbm", "label": "Marvell Custom HBM Compute Architecture", "url": "https://www.marvell.com/products/custom-asic/custom-hbm-compute-architecture.html", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": null, "checked_at": "2026-11-06", "notes": "Architecture-level benefits are vendor-stated; no public named XPU SKU." }, { "id": "ref-marvell-nvlink-fusion", "label": "Marvell joins NVIDIA NVLink Fusion", "url": "https://www.marvell.com/company/newsroom/nvidia-ai-ecosystem-expands-marvell-joins-forces-through-nvlink-fusion.html", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": "2026-03-31", "checked_at": "2026-11-06", "notes": "Partnership capability announcement, not a chip datasheet." } ] }, { "id": "broadcom", "display_name": "Broadcom — custom XPUs", "category": "IC Vendors", "directory_anchor": "Broadcom", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Broadcom_logo.png", "summary": "Broadcom co-designs customer-specific AI XPUs, advanced packaging and high-speed networking. Public evidence supports a custom-silicon platform and multi-generation customer programs; individual customer chip SKUs and full specifications are generally undisclosed.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [ { "id": "broadcom-custom-xpu-platform", "name": "Broadcom Custom XPU Platform", "product_type": "asic", "architecture": "Customer-specific custom AI accelerator; chiplet, HBM and advanced-package co-design", "generation": "Multi-generation custom XPU platform", "family": "Broadcom Custom Silicon", "market_segment": "Hyperscale custom AI accelerators", "availability": "production", "form_factor": "Customer-specific ASIC / multi-die package", "claim_ids": [ "broadcom-xpu-3d5d", "broadcom-xpu-meta-2nm" ], "availability_history": [ { "status": "announced", "effective_at": "2024-12-05", "evidence_id": "broadcom-xpu-platform", "notes": "Broadcom introduced its 3.5D XDSiP custom-XPU platform." }, { "status": "production", "effective_at": "2026-02-26", "evidence_id": "broadcom-xpu-platform", "notes": "Broadcom announced shipment of a 2nm custom compute SoC built on 3.5D XDSiP; platform-level evidence, not a named customer SKU." } ] } ], "claims": [ { "id": "broadcom-xpu-3d5d", "subject_type": "product", "subject_id": "broadcom-custom-xpu-platform", "topic": "packaging", "statement": "Broadcom's 3.5D XDSiP platform supports multi-die custom XPU configurations integrating compute stacks, I/O chiplets and HBM.", "scope": "Platform architecture; configurations vary by customer design.", "claim_status": "vendor_reported", "evidence_ids": [ "broadcom-xpu-platform" ], "last_reviewed": "2026-11-06" }, { "id": "broadcom-xpu-meta-2nm", "subject_type": "product", "subject_id": "broadcom-custom-xpu-platform", "topic": "process_node", "statement": "Broadcom and Meta announced a multi-generation collaboration to deploy a 2nm AI compute accelerator.", "scope": "Customer-specific Meta MTIA program; not a general Broadcom merchant product.", "claim_status": "vendor_reported", "evidence_ids": [ "broadcom-meta-xpu" ], "last_reviewed": "2026-11-06" } ], "evidence": [ { "id": "broadcom-xpu-platform", "title": "AI Accelerator | XPU | Custom Compute", "url": "https://www.broadcom.com/info/ai/3point5d", "publisher": "Broadcom", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official custom XPU platform page. Platform-level configurations are illustrative/customer-specific; not all are volume products." }, { "id": "broadcom-meta-xpu", "title": "Broadcom and Meta extend partnership for multi-gigawatt custom silicon", "url": "https://www.broadcom.com/company/news/product-releases/64236", "publisher": "Broadcom", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2026-04-14", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official announcement dated 2026-04-14. Describes multi-year collaboration and a 2nm MTIA accelerator; no public chip-level datasheet." } ], "references": [ { "id": "ref-broadcom-1", "label": "OpenAI Jalapeño with Broadcom", "url": "https://openai.com/index/openai-broadcom-jalapeno-inference-chip/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-broadcom-2", "label": "Meta MTIA partnership extended", "url": "https://www.nasdaq.com/press-release/broadcom-announces-extended-partnership-meta-deploy-technology-support-multi", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-broadcom-xpu-platform", "label": "Broadcom 3.5D XDSiP custom XPU platform", "url": "https://www.broadcom.com/info/ai/3point5d", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": null, "checked_at": "2026-11-06", "notes": "Customer-specific platform, not a universal merchant SKU." }, { "id": "ref-broadcom-meta-xpu", "label": "Broadcom–Meta multi-generation XPU partnership", "url": "https://www.broadcom.com/company/news/product-releases/64236", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": "2026-04-14", "checked_at": "2026-11-06", "notes": "2nm MTIA collaboration announcement; chip specifications remain undisclosed." } ] }, { "id": "google", "display_name": "Google — TPU lineage", "category": "Tech Giants & HPC Vendors", "directory_anchor": "Google", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Google_logo.png", "summary": "Google invented the modern custom-AI-ASIC pattern with TPU v1 (2015) for production inference, then opened Cloud TPU for external training. Each generation scaled systolic MXUs, HBM, and pod interconnect; v4/v5 pods trained many Google foundation models, while Trillium (v6e) and Ironwood (v7) address GenAI train/serve economics. Edge TPU (Coral) and Pixel Tensor are related but separate product lines.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [ { "id": "tpu7x-ironwood", "name": "Google TPU7x (Ironwood)", "product_type": "asic", "architecture": "TPU7x / Ironwood", "generation": "7th-generation TPU", "market_segment": "Google Cloud AI training and inference", "availability": "shipping", "claim_ids": [ "tpu7x-memory-capacity", "tpu7x-memory-bandwidth", "tpu7x-ici-bandwidth", "tpu7x-bf16-compute", "tpu7x-fp8-compute", "tpu7x-pod-scale", "tpu7x-architecture" ], "compatibility_platform_ids": [ "google-tpu" ] }, { "id": "tpu-v6e-trillium", "name": "Google Cloud TPU v6e (Trillium)", "product_type": "asic", "architecture": "TPU v6e / Trillium", "generation": "6th-generation TPU", "family": "Google Cloud TPU", "market_segment": "Cloud AI training, fine-tuning and serving", "availability": "shipping", "form_factor": "Cloud TPU accelerator chip", "claim_ids": [ "tpu-v6e-memory-capacity", "tpu-v6e-memory-bandwidth", "tpu-v6e-bf16-peak", "tpu-v6e-ici-bandwidth", "tpu-v6e-pod-scale" ], "compatibility_platform_ids": [ "google-tpu" ] } ], "claims": [ { "id": "tpu7x-memory-capacity", "subject_type": "product", "subject_id": "tpu7x-ironwood", "topic": "memory_capacity", "statement": "Google Cloud lists 192 GiB of TPU memory per TPU7x (Ironwood) chip.", "value": 192, "unit": "GiB", "scope": "Per TPU7x chip, as published in Google Cloud's TPU version table.", "claim_status": "vendor_reported", "evidence_ids": [ "google-tpu7x-ironwood-docs-2026" ], "last_reviewed": "2026-11-06", "notes": "Cloud product documentation; preserve GiB units.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" } }, { "id": "tpu7x-memory-bandwidth", "subject_type": "product", "subject_id": "tpu7x-ironwood", "topic": "memory_bandwidth", "statement": "Google Cloud lists 7,380 GB/s TPU memory bandwidth for TPU7x (Ironwood).", "value": 7380, "unit": "GB/s", "scope": "Per TPU7x chip, as published in Google Cloud's TPU version table.", "claim_status": "vendor_reported", "evidence_ids": [ "google-tpu7x-ironwood-docs-2026" ], "last_reviewed": "2026-11-06", "notes": "Vendor-published specification.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" } }, { "id": "tpu7x-ici-bandwidth", "subject_type": "product", "subject_id": "tpu7x-ironwood", "topic": "interconnect", "statement": "Google Cloud lists 1,200 GB/s interconnect (ICI) bandwidth per TPU7x chip.", "value": 1200, "unit": "GB/s", "scope": "Per TPU7x chip; ICI bandwidth, not data-center network bandwidth.", "claim_status": "vendor_reported", "evidence_ids": [ "google-tpu7x-ironwood-docs-2026" ], "last_reviewed": "2026-11-06", "notes": "Vendor-published ICI figure; do not compare directly with Ethernet or InfiniBand bandwidth.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "interconnect", "directionality": "bidirectional" } }, { "id": "tpu7x-bf16-compute", "subject_type": "product", "subject_id": "tpu7x-ironwood", "topic": "compute", "statement": "Google Cloud lists 2,307 TFLOPs peak BF16 compute per TPU7x chip.", "value": 2307, "unit": "TFLOPs BF16", "scope": "Per TPU7x chip; peak compute figure in Google Cloud's TPU version table.", "claim_status": "vendor_reported", "evidence_ids": [ "google-tpu7x-ironwood-docs-2026" ], "last_reviewed": "2026-11-06", "notes": "Vendor theoretical peak; retain precision and chip-level scope.", "metric_context": { "metric_type": "theoretical_peak", "measurement_scope": "chip", "operation": "matrix", "precision": "BF16", "sparsity": "dense" } }, { "id": "tpu7x-fp8-compute", "subject_type": "product", "subject_id": "tpu7x-ironwood", "topic": "compute", "statement": "Google Cloud lists 4,614 TFLOPs peak FP8 compute per TPU7x chip.", "value": 4614, "unit": "TFLOPs FP8", "scope": "Per TPU7x chip; peak compute figure in Google Cloud's TPU version table.", "claim_status": "vendor_reported", "evidence_ids": [ "google-tpu7x-ironwood-docs-2026" ], "last_reviewed": "2026-11-06", "notes": "Vendor theoretical peak; retain precision and chip-level scope.", "metric_context": { "metric_type": "theoretical_peak", "measurement_scope": "chip", "operation": "matrix", "precision": "FP8", "sparsity": "dense" } }, { "id": "tpu7x-pod-scale", "subject_type": "product", "subject_id": "tpu7x-ironwood", "topic": "deployment", "statement": "Google Cloud lists up to 9,216 TPU7x chips per pod.", "value": 9216, "unit": "chips per pod", "scope": "Maximum TPU7x pod scale in the Google Cloud TPU version table.", "claim_status": "vendor_reported", "evidence_ids": [ "google-tpu7x-ironwood-docs-2026" ], "last_reviewed": "2026-11-06", "notes": "Pod-scale specification; actual available slice and deployment options are product/configuration dependent.", "metric_context": { "metric_type": "specification", "measurement_scope": "pod", "operation": "system_configuration" } }, { "id": "tpu7x-architecture", "topic": "architecture", "statement": "Google Cloud identifies TPU7x as the Ironwood TPU version.", "value": "TPU7x / Ironwood", "scope": "Google Cloud TPU version and machine-series nomenclature.", "notes": "Official Google Cloud documentation.", "subject_type": "product", "subject_id": "tpu7x-ironwood", "claim_status": "vendor_reported", "evidence_ids": [ "google-tpu7x-ironwood-docs-2026" ], "last_reviewed": "2026-11-06" }, { "id": "tpu-v6e-memory-capacity", "subject_type": "product", "subject_id": "tpu-v6e-trillium", "topic": "memory_capacity", "statement": "Google Cloud specifies 32 GB of HBM per TPU v6e chip.", "value": 32, "unit": "GB HBM", "scope": "Per TPU v6e chip.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "google-tpu-v6e-specs" ], "last_reviewed": "2026-11-05" }, { "id": "tpu-v6e-memory-bandwidth", "subject_type": "product", "subject_id": "tpu-v6e-trillium", "topic": "memory_bandwidth", "statement": "Google Cloud specifies 1,638 GB/s HBM bandwidth per TPU v6e chip.", "value": 1638, "unit": "GB/s", "scope": "Per TPU v6e chip.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "google-tpu-v6e-specs" ], "last_reviewed": "2026-11-05" }, { "id": "tpu-v6e-bf16-peak", "subject_type": "product", "subject_id": "tpu-v6e-trillium", "topic": "compute", "statement": "Google Cloud specifies 918 TFLOPs peak BF16 compute per TPU v6e chip.", "value": 918, "unit": "TFLOPs BF16", "scope": "Per TPU v6e chip; peak compute specification.", "metric_context": { "metric_type": "theoretical_peak", "measurement_scope": "chip", "operation": "matrix", "precision": "BF16", "sparsity": "dense" }, "claim_status": "vendor_reported", "evidence_ids": [ "google-tpu-v6e-specs" ], "last_reviewed": "2026-11-05" }, { "id": "tpu-v6e-ici-bandwidth", "subject_type": "product", "subject_id": "tpu-v6e-trillium", "topic": "interconnect", "statement": "Google Cloud specifies 800 GB/s bidirectional ICI bandwidth per TPU v6e chip.", "value": 800, "unit": "GB/s", "scope": "Per TPU v6e chip; bidirectional inter-chip interconnect bandwidth.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "interconnect", "directionality": "bidirectional" }, "claim_status": "vendor_reported", "evidence_ids": [ "google-tpu-v6e-specs" ], "last_reviewed": "2026-11-05" }, { "id": "tpu-v6e-pod-scale", "subject_type": "product", "subject_id": "tpu-v6e-trillium", "topic": "deployment", "statement": "Google Cloud specifies a 256-chip TPU v6e Pod.", "value": 256, "unit": "chips per Pod", "scope": "Maximum documented TPU v6e Pod size.", "metric_context": { "metric_type": "specification", "measurement_scope": "pod", "operation": "system_configuration" }, "claim_status": "vendor_reported", "evidence_ids": [ "google-tpu-v6e-specs" ], "last_reviewed": "2026-11-05" } ], "evidence": [ { "id": "google-cloud-tpu7x-specs", "title": "Google Cloud — Understand TPUs", "url": "https://docs.cloud.google.com/docs/compute-area/tpus?hl=en", "publisher": "Google Cloud", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-05", "review_status": "reviewed", "notes": "Official vendor documentation checked on 2026-11-05. These are vendor-published specifications, not independent benchmark measurements. The TPU7x values are taken from the published TPU version and machine-series table." }, { "id": "google-tpu-v6e-specs", "title": "Google Cloud TPU v6e (Trillium) architecture and specifications", "url": "https://docs.cloud.google.com/tpu/docs/v6e", "publisher": "Google Cloud", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-05", "review_status": "reviewed", "notes": "Official Google Cloud TPU documentation. Values are per TPU v6e chip unless the scope explicitly says Pod." }, { "id": "google-tpu7x-ironwood-docs-2026", "title": "Google Cloud TPU7x (Ironwood) architecture and specifications", "url": "https://docs.cloud.google.com/tpu/docs/tpu7x", "publisher": "Google Cloud", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official Google Cloud TPU7x documentation; 192 GiB HBM, 7,380 GB/s HBM bandwidth, and 9,216 chips per pod. TPU7x is generally available as of 2026-03-31." } ], "references": [ { "id": "ref-google-1", "label": "Ironwood (TPU7x) GA", "url": "https://docs.cloud.google.com/tpu/docs/release-notes", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-google-2", "label": "Ironwood for the age of inference", "url": "https://blog.google/innovation-and-ai/infrastructure-and-cloud/google-cloud/ironwood-google-tpu-things-to-know/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-google-3", "label": "10 years of TPU", "url": "https://cloud.google.com/transform/ai-specialized-chips-tpu-history-gen-ai", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-google-4", "label": "v6e docs", "url": "https://docs.cloud.google.com/tpu/docs/v6e", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-google-5", "label": "Cloud TPU", "url": "https://cloud.google.com/tpu", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-google-6", "label": "Edge TPU", "url": "https://cloud.google.com/edge-tpu/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-google-tpu7x-ironwood-2026", "label": "TPU7x Ironwood architecture documentation", "url": "https://docs.cloud.google.com/tpu/docs/tpu7x", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": null, "checked_at": "2026-11-06", "notes": "Reviewed against current TPU7x product documentation." } ] }, { "id": "amazon-aws", "display_name": "Amazon AWS — Trainium & Inferentia", "category": "Tech Giants & HPC Vendors", "directory_anchor": "Amazon_AWS", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Amazon_AWS.png", "summary": "AWS builds first-party AI silicon for EC2: Inferentia for inference and Trainium for training, compiled via the Neuron SDK. Inferentia1/2 lowered LLM serving cost on Inf1/Inf2; Trainium1 and Trainium2 (Trn1/Trn2) plus UltraServers with NeuronLink scale-up target foundation-model training and large inference inside AWS regions—often co-designed with partners such as Marvell/Annapurna.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [ { "id": "trainium2", "name": "AWS Trainium2", "product_type": "asic", "architecture": "NeuronCore-v3", "generation": "2nd-generation Trainium", "family": "AWS Trainium", "market_segment": "AWS cloud AI training and inference", "availability": "shipping", "form_factor": "AWS EC2 accelerator chip", "claim_ids": [ "trainium2-memory-capacity", "trainium2-memory-bandwidth", "trainium2-fp8-dense", "trainium2-fp8-sparse", "trainium2-neuroncores" ], "compatibility_platform_ids": [ "aws-trainium" ] }, { "id": "trainium3", "name": "AWS Trainium3", "product_type": "asic", "architecture": "NeuronCore-v4", "generation": "4th-generation Trainium", "family": "AWS Trainium", "process_node": "TSMC 3nm", "market_segment": "AWS cloud AI training and inference", "availability": "shipping", "form_factor": "AWS EC2 accelerator chip", "announced_at": "2025-12-02", "first_available_at": "2025-12-02", "claim_ids": [ "trainium3-memory-capacity", "trainium3-memory-bandwidth", "trainium3-fp8-peak", "trainium3-bf16-peak", "trainium3-neuronlink" ], "compatibility_platform_ids": [ "aws-trainium" ] } ], "claims": [ { "id": "trainium2-memory-capacity", "subject_type": "product", "subject_id": "trainium2", "topic": "memory_capacity", "statement": "AWS specifies 96 GiB of HBM per Trainium2 chip.", "value": 96, "unit": "GiB HBM", "scope": "Per Trainium2 chip.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "aws-trainium2-specs" ], "last_reviewed": "2026-11-05" }, { "id": "trainium2-memory-bandwidth", "subject_type": "product", "subject_id": "trainium2", "topic": "memory_bandwidth", "statement": "AWS specifies 2.9 TB/s HBM bandwidth per Trainium2 chip.", "value": 2.9, "unit": "TB/s", "scope": "Per Trainium2 chip.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "aws-trainium2-specs" ], "last_reviewed": "2026-11-05" }, { "id": "trainium2-fp8-dense", "subject_type": "product", "subject_id": "trainium2", "topic": "compute", "statement": "AWS specifies up to 1.3 PFLOPs dense FP8 compute per Trainium2 chip.", "value": 1.3, "unit": "PFLOPs FP8", "scope": "Per Trainium2 chip; dense FP8 peak.", "metric_context": { "metric_type": "theoretical_peak", "measurement_scope": "chip", "operation": "matrix", "precision": "FP8", "sparsity": "dense" }, "claim_status": "vendor_reported", "evidence_ids": [ "aws-trainium2-specs" ], "last_reviewed": "2026-11-05" }, { "id": "trainium2-fp8-sparse", "subject_type": "product", "subject_id": "trainium2", "topic": "compute", "statement": "AWS specifies up to 5.2 PFLOPs sparse FP8 compute per Trainium2 chip.", "value": 5.2, "unit": "PFLOPs FP8", "scope": "Per Trainium2 chip; sparse FP8 peak.", "metric_context": { "metric_type": "theoretical_peak", "measurement_scope": "chip", "operation": "matrix", "precision": "FP8", "sparsity": "structured_sparse" }, "claim_status": "vendor_reported", "evidence_ids": [ "aws-trainium2-specs" ], "last_reviewed": "2026-11-05", "notes": "Sparse result is kept separate from dense FP8; do not compare directly with dense-only figures." }, { "id": "trainium2-neuroncores", "subject_type": "product", "subject_id": "trainium2", "topic": "architecture", "statement": "AWS specifies eight NeuronCore-v3 cores per Trainium2 chip.", "value": 8, "unit": "NeuronCore-v3 cores", "scope": "Per Trainium2 chip.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "system_configuration" }, "claim_status": "vendor_reported", "evidence_ids": [ "aws-trainium2-specs" ], "last_reviewed": "2026-11-05" }, { "id": "trainium3-memory-capacity", "subject_type": "product", "subject_id": "trainium3", "topic": "memory_capacity", "statement": "AWS specifies 144 GiB of device memory per Trainium3 chip.", "value": 144, "unit": "GiB HBM3e", "scope": "Per Trainium3 chip.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "aws-trainium3-ec2-product-2026" ], "last_reviewed": "2026-11-06" }, { "id": "trainium3-memory-bandwidth", "subject_type": "product", "subject_id": "trainium3", "topic": "memory_bandwidth", "statement": "AWS specifies 4.9 TB/s device-memory bandwidth per Trainium3 chip.", "value": 4.9, "unit": "TB/s", "scope": "Per Trainium3 chip.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "aws-trainium3-ec2-product-2026" ], "last_reviewed": "2026-11-06" }, { "id": "trainium3-fp8-peak", "subject_type": "product", "subject_id": "trainium3", "topic": "compute", "statement": "AWS specifies 2,517 TFLOPs peak FP8 compute per Trainium3 chip.", "value": 2517, "unit": "TFLOPs FP8", "scope": "Per Trainium3 chip; peak FP8 specification.", "metric_context": { "metric_type": "theoretical_peak", "measurement_scope": "chip", "operation": "matrix", "precision": "FP8", "sparsity": "dense" }, "claim_status": "vendor_reported", "evidence_ids": [ "aws-trainium3-ec2-product-2026" ], "last_reviewed": "2026-11-06" }, { "id": "trainium3-bf16-peak", "subject_type": "product", "subject_id": "trainium3", "topic": "compute", "statement": "AWS specifies 671 TFLOPs BF16/FP16/TF32 compute per Trainium3 chip.", "value": 671, "unit": "TFLOPs BF16/FP16/TF32", "scope": "Per Trainium3 chip; AWS groups these formats in the architecture table.", "metric_context": { "metric_type": "theoretical_peak", "measurement_scope": "chip", "operation": "matrix", "precision": "mixed", "sparsity": "dense" }, "claim_status": "vendor_reported", "evidence_ids": [ "aws-trainium3-ec2-product-2026" ], "last_reviewed": "2026-11-06", "notes": "The source reports a combined BF16/FP16/TF32 figure; preserve the combined source wording rather than assigning it to a single precision." }, { "id": "trainium3-neuronlink", "subject_type": "product", "subject_id": "trainium3", "topic": "interconnect", "statement": "AWS specifies 2.56 TB/s NeuronLink-v4 bandwidth per Trainium3 device.", "value": 2.56, "unit": "TB/s", "scope": "Per Trainium3 device.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "interconnect", "directionality": "unspecified" }, "claim_status": "vendor_reported", "evidence_ids": [ "aws-trainium3-ec2-product-2026" ], "last_reviewed": "2026-11-06" } ], "evidence": [ { "id": "aws-trainium2-specs", "title": "Amazon EC2 Trn2 instances and Trn2 UltraServers", "url": "https://aws.amazon.com/blogs/aws/amazon-ec2-trn2-instances-and-trn2-ultraservers-for-aiml-training-and-inference-is-now-available/", "publisher": "Amazon Web Services", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-05", "review_status": "reviewed", "notes": "Official AWS News Blog. Trainium2 figures are per chip; dense and sparse FP8 performance are separate claims." }, { "id": "aws-trainium3-architecture", "title": "AWS Neuron — Trainium3 Architecture", "url": "https://awsdocs-neuron.readthedocs-hosted.com/en/latest/about-neuron/arch/neuron-hardware/trainium3.html", "publisher": "AWS Neuron", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-05", "review_status": "reviewed", "notes": "Official AWS Neuron architecture documentation. It distinguishes FP8, MXFP8/MXFP4, BF16 and sparse modes; only like-for-like modes should be compared." }, { "id": "aws-trainium3-ec2-product-2026", "title": "Amazon EC2 Trn3 UltraServers", "url": "https://aws.amazon.com/ec2/instance-types/trn3/", "publisher": "Amazon Web Services", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official AWS product documentation. Trainium3 is listed with 144 GiB HBM3e and 4.9 TB/s bandwidth per chip; UltraServer aggregates 144 chips." } ], "references": [ { "id": "ref-amazon-aws-1", "label": "EC2 Trn3 UltraServers (Trainium3)", "url": "https://aws.amazon.com/about-aws/whats-new/2025/12/amazon-ec2-trn3-ultraservers/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-amazon-aws-2", "label": "Trainium3 UltraServers details", "url": "https://press.aboutamazon.com/2025/12/trainium3-ultraservers-now-available-enabling-customers-to-train-and-deploy-ai-models-faster-at-lower-cost", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-aws-trainium3-2026", "label": "Trainium3 / Trn3 UltraServer product documentation", "url": "https://aws.amazon.com/ec2/instance-types/trn3/", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": null, "checked_at": "2026-11-06", "notes": "Reviewed against AWS current product documentation." } ] }, { "id": "microsoft", "display_name": "Microsoft — Azure Maia", "category": "Tech Giants & HPC Vendors", "directory_anchor": "Microsoft", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Microsoft_logo.png", "summary": "Microsoft entered custom AI silicon with Azure Maia (accelerator) and Cobalt (Arm CPU) to optimize Azure OpenAI / Copilot economics. Maia 100 (5nm, advanced packaging) is co-designed for Azure AI cloud workloads with a PyTorch/ONNX Runtime software path; subsequent Maia generations are expected to deepen rack-level integration with Azure networking and cooling.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [ { "id": "maia100", "name": "Microsoft Azure Maia 100", "product_type": "asic", "architecture": "Microsoft Maia 100", "generation": "Maia 100", "family": "Azure Maia", "process_node": "TSMC N5", "market_segment": "Azure cloud AI training and inference", "availability": "shipping", "form_factor": "Azure cloud accelerator", "claim_ids": [ "maia100-memory-capacity", "maia100-memory-bandwidth", "maia100-provisioned-power", "maia100-process" ], "compatibility_platform_ids": [ "microsoft-maia" ] }, { "id": "maia200", "name": "Microsoft Azure Maia 200", "product_type": "asic", "architecture": "Microsoft Maia 200", "generation": "Maia 200", "family": "Azure Maia", "process_node": "TSMC 3nm", "market_segment": "Azure cloud generative AI inference", "availability": "announced", "form_factor": "Azure cloud inference accelerator", "announced_at": "2026-01-26", "claim_ids": [ "maia200-memory-capacity", "maia200-memory-bandwidth", "maia200-sram-capacity", "maia200-process" ], "compatibility_platform_ids": [ "microsoft-maia" ] }, { "id": "maia300", "name": "Microsoft Azure Maia 300", "product_type": "asic", "architecture": "Microsoft Maia 300 dataflow accelerator", "generation": "Maia 300", "family": "Azure Maia", "market_segment": "Azure AI inference and long-context workloads", "availability": "announced", "form_factor": "950 W liquid-cooled accelerator; rack-scale 96-accelerator system", "announced_at": "2026-10-12", "system_configuration": "96 accelerators per rack; 167 kW rack power envelope", "claim_ids": [ "maia300-hbm-bandwidth", "maia300-tdp", "maia300-rack-count", "maia300-rack-hbm", "maia300-rack-bandwidth" ], "compatibility_platform_ids": [ "microsoft-maia" ] } ], "claims": [ { "id": "maia100-memory-capacity", "subject_type": "product", "subject_id": "maia100", "topic": "memory_capacity", "statement": "Microsoft specifies 64 GB of HBM2E memory for Maia 100.", "value": 64, "unit": "GB HBM2E", "scope": "Per Maia 100 accelerator.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "microsoft-maia100-specs" ], "last_reviewed": "2026-11-05" }, { "id": "maia100-memory-bandwidth", "subject_type": "product", "subject_id": "maia100", "topic": "memory_bandwidth", "statement": "Microsoft specifies 1.8 TB/s HBM bandwidth for Maia 100.", "value": 1.8, "unit": "TB/s", "scope": "Per Maia 100 accelerator.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "microsoft-maia100-specs" ], "last_reviewed": "2026-11-05" }, { "id": "maia100-provisioned-power", "subject_type": "product", "subject_id": "maia100", "topic": "power", "statement": "Microsoft says Maia 100 is designed for up to 700 W TDP and provisioned at 500 W.", "value": 500, "unit": "W provisioned", "scope": "Per Maia 100 accelerator; provisioned operating configuration, not design maximum.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "power", "configuration": "700 W design TDP; 500 W provisioned" }, "claim_status": "vendor_reported", "evidence_ids": [ "microsoft-maia100-specs" ], "last_reviewed": "2026-11-05" }, { "id": "maia100-process", "subject_type": "product", "subject_id": "maia100", "topic": "process_node", "statement": "Microsoft identifies TSMC N5 as the Maia 100 process technology.", "value": "TSMC N5", "scope": "Maia 100 SoC process technology.", "claim_status": "vendor_reported", "evidence_ids": [ "microsoft-maia100-specs" ], "last_reviewed": "2026-11-05" }, { "id": "maia200-memory-capacity", "subject_type": "product", "subject_id": "maia200", "topic": "memory_capacity", "statement": "Microsoft specifies 216 GB of HBM3e memory for Maia 200.", "value": 216, "unit": "GB HBM3e", "scope": "Per Maia 200 accelerator.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "microsoft-maia200-specs" ], "last_reviewed": "2026-11-05" }, { "id": "maia200-memory-bandwidth", "subject_type": "product", "subject_id": "maia200", "topic": "memory_bandwidth", "statement": "Microsoft specifies 7 TB/s HBM bandwidth for Maia 200.", "value": 7, "unit": "TB/s", "scope": "Per Maia 200 accelerator.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "microsoft-maia200-specs" ], "last_reviewed": "2026-11-05" }, { "id": "maia200-sram-capacity", "subject_type": "product", "subject_id": "maia200", "topic": "memory_capacity", "statement": "Microsoft specifies 272 MB of on-chip SRAM for Maia 200.", "value": 272, "unit": "MB SRAM", "scope": "On-chip SRAM per Maia 200 accelerator.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "microsoft-maia200-specs" ], "last_reviewed": "2026-11-05" }, { "id": "maia200-process", "subject_type": "product", "subject_id": "maia200", "topic": "process_node", "statement": "Microsoft identifies TSMC 3nm as the Maia 200 process technology.", "value": "TSMC 3nm", "scope": "Maia 200 SoC process technology.", "claim_status": "vendor_reported", "evidence_ids": [ "microsoft-maia200-specs" ], "last_reviewed": "2026-11-05" }, { "id": "maia300-hbm-bandwidth", "subject_type": "product", "subject_id": "maia300", "topic": "memory_bandwidth", "statement": "Microsoft lists 18.0 TB/s peak HBM4 bandwidth for Maia 300.", "value": 18, "unit": "TB/s", "scope": "Per Maia 300 accelerator.", "claim_status": "vendor_reported", "evidence_ids": [ "microsoft-maia300-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" } }, { "id": "maia300-tdp", "subject_type": "product", "subject_id": "maia300", "topic": "power", "statement": "Microsoft lists a 950 W TDP for Maia 300.", "value": 950, "unit": "W TDP", "scope": "Per Maia 300 accelerator; vendor-designated TDP.", "claim_status": "vendor_reported", "evidence_ids": [ "microsoft-maia300-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "power" } }, { "id": "maia300-rack-count", "subject_type": "product", "subject_id": "maia300", "topic": "system_scale", "statement": "Microsoft describes a Maia 300 rack with 96 accelerators.", "value": 96, "unit": "accelerators", "scope": "Per Maia 300 rack.", "claim_status": "vendor_reported", "evidence_ids": [ "microsoft-maia300-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "rack", "operation": "system_configuration" } }, { "id": "maia300-rack-hbm", "subject_type": "product", "subject_id": "maia300", "topic": "memory_capacity", "statement": "Microsoft lists 27.6 TB aggregate HBM capacity in a 96-accelerator Maia 300 rack.", "value": 27.6, "unit": "TB HBM", "scope": "Aggregate per 96-accelerator rack.", "claim_status": "vendor_reported", "evidence_ids": [ "microsoft-maia300-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "rack", "operation": "memory" } }, { "id": "maia300-rack-bandwidth", "subject_type": "product", "subject_id": "maia300", "topic": "memory_bandwidth", "statement": "Microsoft lists 1.7 PB/s aggregate HBM bandwidth in a Maia 300 rack.", "value": 1.7, "unit": "PB/s", "scope": "Aggregate per 96-accelerator rack.", "claim_status": "vendor_reported", "evidence_ids": [ "microsoft-maia300-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "rack", "operation": "memory" } } ], "evidence": [ { "id": "microsoft-maia100-specs", "title": "Inside Maia 100 — Microsoft Azure Infrastructure Blog", "url": "https://techcommunity.microsoft.com/blog/azureinfrastructureblog/inside-maia-100-revolutionizing-ai-workloads-with-microsofts-custom-ai-accelerat/4229118", "publisher": "Microsoft", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-05", "review_status": "reviewed", "notes": "Official Microsoft engineering article. It distinguishes 700 W design TDP from the 500 W provisioned operating configuration." }, { "id": "microsoft-maia200-specs", "title": "Maia 200: The AI accelerator built for inference", "url": "https://blogs.microsoft.com/blog/2026/01/26/maia-200-the-ai-accelerator-built-for-inference/", "publisher": "Microsoft", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2026-01-26", "checked_at": "2026-11-05", "review_status": "reviewed", "notes": "Official Microsoft announcement. HBM capacity, bandwidth, SRAM and process node are vendor-reported specifications." }, { "id": "microsoft-maia300-2026", "title": "Microsoft to expand Azure Maia system to multi-gigawatt deployments", "url": "https://blogs.microsoft.com/blog/2026/10/12/microsoft-to-expand-azure-maia-system-to-multi-gigawatt-deployments/", "publisher": "Microsoft", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2026-10-12", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official Microsoft announcement. Maia 300 production deployments are stated to begin in 2027; rack-level totals are not per-chip specifications." } ], "references": [ { "id": "ref-microsoft-1", "label": "Maia 200 inference accelerator", "url": "https://blogs.microsoft.com/blog/2026/01/26/maia-200-the-ai-accelerator-built-for-inference/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-microsoft-2", "label": "Maia 200 Azure rollout", "url": "https://news.microsoft.com/source/emea/2026/01/microsoft-introduces-maia-200-new-inference-accelerator-enhances-ai-performance-in-azure/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-microsoft-maia300", "label": "Maia 300 product and rack architecture", "url": "https://blogs.microsoft.com/blog/2026/10/12/microsoft-to-expand-azure-maia-system-to-multi-gigawatt-deployments/", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": "2026-10-12", "checked_at": "2026-11-06", "notes": "Reviewed against Microsoft official announcement; production deployment timing remains 2027." } ] }, { "id": "open-ai", "display_name": "OpenAI — custom Intelligence Processors", "category": "Tech Giants & HPC Vendors", "directory_anchor": "OpenAI", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/OpenAI_logo.png", "summary": "Long dependent on NVIDIA GPUs (and Azure capacity), OpenAI moved into custom inference silicon to cut serving cost and diversify supply. Jalapeño—co-developed with Broadcom—is the first “Intelligence Processor,” optimized for LLM inference rather than general training, as the opening move in a multi-generation, multi-gigawatt Broadcom collaboration.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-open-ai-1", "label": "Jalapeño LLM inference chip", "url": "https://openai.com/index/openai-broadcom-jalapeno-inference-chip/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "anthropic", "display_name": "Anthropic — multi-hardware compute", "category": "Tech Giants & HPC Vendors", "directory_anchor": "Anthropic", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Anthropic_logo.png", "summary": "Anthropic does not tape out a merchant chip brand; it co-designs capacity across AWS Trainium (Project Rainier), Google TPUs (Broadcom-implemented), and NVIDIA GPUs. The strategy is deliberate multi-sourcing for Claude training and serving at gigawatt scale, with long-term TPU commitments expanding through 2027+.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-anthropic-1", "label": "Google & Broadcom compute partnership", "url": "https://www.anthropic.com/news/google-broadcom-partnership-compute", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "apple", "display_name": "Apple — Neural Engine & Apple silicon AI", "category": "Tech Giants & HPC Vendors", "directory_anchor": "Apple", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Apple_logo.png", "summary": "Apple’s on-device AI runs on the Neural Engine and, increasingly, GPU Neural Accelerators inside Apple silicon—not discrete datacenter GPUs. From A11’s first Neural Engine through M1–M4, Apple scaled unified-memory ML performance for privacy-preserving inference; M5 (2025) and M5 Pro/Max (2026) explicitly target Apple Intelligence and local LLM/creative AI workflows.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-apple-1", "label": "Apple M5", "url": "https://www.apple.com/newsroom/2025/10/apple-unleashes-m5-the-next-big-leap-in-ai-performance-for-apple-silicon/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-apple-2", "label": "M5 Pro and M5 Max", "url": "https://www.apple.com/newsroom/2026/03/apple-debuts-m5-pro-and-m5-max-to-supercharge-the-most-demanding-pro-workflows/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "alibaba", "display_name": "Alibaba — T-Head PPU", "category": "Tech Giants & HPC Vendors", "directory_anchor": "Alibaba", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/alibaba_logo.png", "summary": "Alibaba’s T-Head unit designs cloud AI accelerators under the Zhenwu / PPU family for Alibaba Cloud and external customers as a domestic GPU-class alternative. After Zhenwu 810E-class SKUs, Zhenwu M890 (2026) raises HBM capacity and chip-to-chip bandwidth for agentic train/infer, paired with Panjiu AL128 servers, ICN Switch networking, and the SAIL software stack.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-alibaba-1", "label": "Zhenwu M890 AI chip", "url": "https://www.alibabacloud.com/blog/alibaba-unveils-new-ai-chip-flagship-model-and-rebuilt-cloud-stack-ai-for-agentic-era_603151", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-alibaba-2", "label": "T-Head scale shipments", "url": "https://thenextweb.com/news/alibaba-zhenwu-m890-t-head-china-ai-chip-nvidia", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "baidu", "display_name": "Baidu — Kunlunxin", "category": "Tech Giants & HPC Vendors", "directory_anchor": "Baidu", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Baidu_logo.png", "summary": "Baidu’s Kunlunxin (昆仑芯) GPUs underpin ERNIE and Baidu Cloud AI services. From earlier Kunlun generations through P800-class training/inference cards, Baidu has iterated a full stack (hardware + software) as a China-domestic alternative for large-model workloads.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-baidu-1", "label": "Tianchi 256-card supernode", "url": "https://www.jiemian.com/article/14421027.html", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "tencent-cloud", "display_name": "Tencent Cloud — Zixiao / custom AI", "category": "Tech Giants & HPC Vendors", "directory_anchor": "Tencent_Cloud", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Tencent_Cloud_logo.png", "summary": "Tencent deploys proprietary Zixiao-class and partner AI accelerators across Tencent Cloud for recommendation, multimodal, and LLM train/infer inside its China footprint—part of a broader mix that also includes merchant GPUs where available.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [] }, { "id": "facebook", "display_name": "Meta — MTIA", "category": "Tech Giants & HPC Vendors", "directory_anchor": "Facebook", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/facebook_logo.png", "summary": "Meta’s MTIA (Meta Training and Inference Accelerator) is an in-house family for ranking, recommendation, and increasingly generative workloads at hyperscale. Built with Broadcom as implementation partner, MTIA has moved to a rapid multi-generation chiplet cadence (MTIA 300–500 class messaging) aimed at Meta’s production AI fleet rather than merchant sale.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [ { "id": "mtia-v2", "name": "Meta MTIA v2", "product_type": "asic", "architecture": "Meta MTIA v2", "generation": "MTIA v2", "family": "Meta MTIA", "market_segment": "Ranking and recommendation inference", "availability": "announced", "form_factor": "Meta data-center accelerator", "claim_ids": [ "mtia-v2-target-workload" ], "compatibility_platform_ids": [ "meta-mtia" ] }, { "id": "mtia-300", "name": "Meta MTIA 300", "product_type": "asic", "architecture": "MTIA 300 with integrated NIC chiplets and communication offload", "generation": "MTIA 300", "family": "Meta MTIA", "market_segment": "Ranking and recommendation model training", "availability": "production", "form_factor": "Meta data-center accelerator", "announced_at": "2026-08-24", "claim_ids": [ "mtia300-message-engines", "mtia300-pe-grid", "mtia300-reduction-throughput", "mtia300-nic-chiplets" ], "compatibility_platform_ids": [ "meta-mtia" ] }, { "id": "mtia300", "name": "Meta MTIA 300", "product_type": "asic", "architecture": "MTIA 300 with integrated network chiplets and communication-offload engines", "generation": "MTIA 300", "family": "Meta MTIA", "market_segment": "Training and inference for ranking and recommendation models", "availability": "production", "form_factor": "Data-center accelerator package", "claim_ids": [ "mtia300-hbm-capacity", "mtia300-io-bandwidth", "mtia300-nmc-reduction-throughput", "mtia300-me-count" ], "compatibility_platform_ids": [ "meta-mtia" ] } ], "claims": [ { "id": "mtia-v2-target-workload", "subject_type": "product", "subject_id": "mtia-v2", "topic": "deployment", "statement": "Meta identifies MTIA v2 as a chip intended to power ranking and recommendation ads models.", "value": "Ranking and recommendation ads models", "scope": "Meta's internal ranking and recommendation workloads.", "claim_status": "vendor_reported", "evidence_ids": [ "meta-mtia-v2-roadmap" ], "last_reviewed": "2026-11-05", "notes": "Meta's article does not publish a complete MTIA v2 numerical specification table; no unreported compute or memory figures are inferred." }, { "id": "mtia300-message-engines", "subject_type": "product", "subject_id": "mtia-300", "topic": "architecture", "statement": "Meta specifies 16 dedicated message engines on MTIA 300 for communication offload.", "value": 16, "unit": "message engines", "scope": "Per MTIA 300 chip.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "system_configuration" }, "claim_status": "vendor_reported", "evidence_ids": [ "meta-mtia300-architecture" ], "last_reviewed": "2026-11-05" }, { "id": "mtia300-pe-grid", "subject_type": "product", "subject_id": "mtia-300", "topic": "architecture", "statement": "Meta describes a 12 x 6 grid of processing elements on MTIA 300.", "value": "12 x 6", "unit": "PE grid", "scope": "On-chip compute grid.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "system_configuration" }, "claim_status": "vendor_reported", "evidence_ids": [ "meta-mtia300-architecture" ], "last_reviewed": "2026-11-05" }, { "id": "mtia300-reduction-throughput", "subject_type": "product", "subject_id": "mtia-300", "topic": "interconnect", "statement": "Meta reports more than 2.8 TB/s aggregate reduction throughput from MTIA 300's near-memory compute blocks.", "value": 2.8, "unit": "TB/s lower bound", "scope": "Aggregate on-chip reduction throughput; greater than the stated lower bound.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "communication", "directionality": "aggregate" }, "claim_status": "vendor_reported", "evidence_ids": [ "meta-mtia300-architecture" ], "last_reviewed": "2026-11-05", "notes": "The source says more than 2.8 TB/s; value is stored as the published lower bound, not an exact measured equality." }, { "id": "mtia300-nic-chiplets", "subject_type": "product", "subject_id": "mtia-300", "topic": "architecture", "statement": "Meta identifies MTIA 300 as its first training chip with built-in NIC chiplets and communication-offloading engines.", "value": "Integrated NIC chiplets and communication offload", "scope": "Chip-level architecture description.", "claim_status": "vendor_reported", "evidence_ids": [ "meta-mtia300-architecture" ], "last_reviewed": "2026-11-05" }, { "id": "mtia300-hbm-capacity", "subject_type": "product", "subject_id": "mtia300", "topic": "memory_capacity", "statement": "Meta specifies 216 GB HBM3E per MTIA 300 accelerator.", "value": 216, "unit": "GB HBM3E", "scope": "Per MTIA 300 accelerator.", "claim_status": "vendor_reported", "evidence_ids": [ "meta-mtia300-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "package", "operation": "memory" } }, { "id": "mtia300-io-bandwidth", "subject_type": "product", "subject_id": "mtia300", "topic": "interconnect", "statement": "Meta specifies 1.2 TB/s total I/O bandwidth from 12 integrated 800 Gbps RDMA NICs.", "value": 1.2, "unit": "TB/s", "scope": "Per MTIA 300 package; aggregate I/O bandwidth from integrated NIC chiplets.", "claim_status": "vendor_reported", "evidence_ids": [ "meta-mtia300-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "package", "operation": "interconnect", "directionality": "aggregate" } }, { "id": "mtia300-nmc-reduction-throughput", "subject_type": "product", "subject_id": "mtia300", "topic": "performance", "statement": "Meta reports more than 2.8 TB/s collective reduction throughput from its near-memory compute engines.", "value": 2.8, "unit": "TB/s", "scope": "Aggregate reduction throughput per MTIA 300 package; vendor-reported architecture figure.", "claim_status": "vendor_reported", "evidence_ids": [ "meta-mtia300-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "vendor_measured", "measurement_scope": "package", "operation": "communication" } }, { "id": "mtia300-me-count", "subject_type": "product", "subject_id": "mtia300", "topic": "architecture", "statement": "Meta specifies 16 dedicated message engines (MEs) for communication offload.", "value": 16, "unit": "message engines", "scope": "Per MTIA 300 package.", "claim_status": "vendor_reported", "evidence_ids": [ "meta-mtia300-2026" ], "last_reviewed": "2026-11-06" } ], "evidence": [ { "id": "meta-mtia-v2-roadmap", "title": "Meta's Infrastructure Evolution and the Advent of AI", "url": "https://engineering.fb.com/2025/09/29/data-infrastructure/metas-infrastructure-evolution-and-the-advent-of-ai/", "publisher": "Engineering at Meta", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2025-09-29", "checked_at": "2026-11-05", "review_status": "reviewed", "notes": "Official Meta engineering article. It identifies MTIA v2 as the chip intended for ranking and recommendation ads models; it does not publish a complete numerical specification table." }, { "id": "meta-mtia300-architecture", "title": "MTIA 300: Meta's First Training Chip with Built-in NICs and Communication-Offloading Engines", "url": "https://engineering.fb.com/2026/08/24/networking-traffic/mtia-300-meta-training-chip-built-in-nics/", "publisher": "Engineering at Meta", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2026-08-24", "checked_at": "2026-11-05", "review_status": "reviewed", "notes": "Official Meta engineering article. It describes the 12x6 processing-element grid, 16 dedicated message engines and more than 2.8 TB/s reduction throughput." }, { "id": "meta-mtia300-2026", "title": "MTIA 300: Meta's first training chip with built-in NICs and communication-offloading engines", "url": "https://engineering.fb.com/2026/08/24/networking-traffic/mtia-300-meta-training-chip-built-in-nics/", "publisher": "Engineering at Meta", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2026-08-24", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official Meta engineering article. It distinguishes per-chip package I/O and reduction throughput from rack-level scale-up/scale-out figures." } ], "references": [ { "id": "ref-facebook-1", "label": "MTIA Iris production September 2026", "url": "https://techcrunch.com/2026/07/09/metas-new-ai-chips-will-begin-production-in-september/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-facebook-2", "label": "Four MTIA chips in two years", "url": "https://ai.meta.com/blog/meta-mtia-scale-ai-chips-for-billions/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-meta-mtia300", "label": "MTIA 300 architecture and communication offload", "url": "https://engineering.fb.com/2026/08/24/networking-traffic/mtia-300-meta-training-chip-built-in-nics/", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": "2026-08-24", "checked_at": "2026-11-06", "notes": "Reviewed against Meta's engineering article; claims are vendor-reported." } ] }, { "id": "tesla", "display_name": "Tesla — HW / AI inference & Dojo", "category": "Tech Giants & HPC Vendors", "directory_anchor": "Tesla", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Tesla_logo.png", "summary": "Tesla designs FSD/AI inference SoCs for vehicles (HW3 → HW4/AI4 → AI5) and pursued Dojo training tiles for internal vision-model training. The vertical stack ties cars, Optimus, and data-center inference together; AI5 is the next major SoC step after AI4, with Dojo3 still on the longer training roadmap.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-tesla-1", "label": "Tesla AI5 taped out", "url": "https://electrek.co/2026/04/15/tesla-ai5-chip-taped-out-musk-ai6-dojo3/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "arm", "display_name": "Arm — Ethos NPU IP", "category": "Traditional IP Vendors", "directory_anchor": "ARM", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/ARM_logo.png", "summary": "Arm licenses Ethos NPU IP alongside Cortex CPUs for edge and IoT SoCs. The Ethos-U micro-NPU line (U55 → U65 → U85) scales MAC arrays and adds transformer operators while keeping the Vela/Ethos toolchain path; larger Ethos-N products address higher-TOPS vision/GenAI in Cortex-A systems.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-arm-1", "label": "Ethos-U85 micro-NPU", "url": "https://www.arm.com/products/silicon-ip-cpu/ethos/ethos-u85", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-arm-2", "label": "Arm C1 / SME2 in flagship SoCs", "url": "https://www.techinsights.com/blog/dimensity-9500-debuts-arm-c1-cores-and-dual-npu", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "synopsys", "display_name": "Synopsys — ARC NPX NPU IP", "category": "Traditional IP Vendors", "directory_anchor": "Synopsys", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Synopsys_logo.png", "summary": "Synopsys DesignWare ARC NPX provides licensable neural processor IP for SoC integrators across automotive, consumer, and infrastructure. The family emphasizes scalable TOPS, functional-safety options, and toolchain continuity for DNN/transformer graphs.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-synopsys-1", "label": "ARC NPX NPU IP", "url": "https://www.synopsys.com/designware-ip/processor-solutions/neural-processing-unit.html", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "imagination", "display_name": "Imagination — NNA IP", "category": "Traditional IP Vendors", "directory_anchor": "Imagination", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Imagination_logo.png", "summary": "Imagination’s PowerVR Neural Network Accelerators (NNA) and GPU+NNA combinations target edge and automotive SoCs. IMG Continuum software maps CNN and transformer-class networks onto the NNA datapaths for licensees.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-imagination-1", "label": "Imagination AI / NNA IP", "url": "https://www.imaginationtech.com/products/ai/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "ceva", "display_name": "CEVA — NeuPro / edge AI IP", "category": "Traditional IP Vendors", "directory_anchor": "CEVA", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/CEVA_logo.png", "summary": "CEVA licenses low-power AI processor IP and DSP/NPU hybrids for real-time embedded, automotive, and IoT inference. NeuPro-class offerings and the CEVA DNN compiler add transformer-capable paths for on-device GenAI and vision.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-ceva-1", "label": "CEVA edge AI / NeuPro IP", "url": "https://www.ceva-dsp.com/app/deep-learning/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "cadence", "display_name": "Cadence — Tensilica AI IP", "category": "Traditional IP Vendors", "directory_anchor": "Cadence", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Cadence_logo.png", "summary": "Cadence Tensilica offers configurable NPU and AI DSP IP for on-device and automotive SoCs. The NeuroWeave toolchain maps modern DNN and transformer graphs onto Tensilica datapaths used widely in vision, audio, and edge GenAI chips.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-cadence-1", "label": "Tensilica AI Platform", "url": "https://www.cadence.com/en_US/home/tools/ip/tensilica-ip/tensilica-ai-platform.html", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "veri-silicon", "display_name": "VeriSilicon — VIP NPU IP", "category": "Traditional IP Vendors", "directory_anchor": "VeriSilicon", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/VeriSilicon_logo.png", "summary": "VeriSilicon provides VIP/Acuity NPU IP plus turnkey ASIC design services, especially strong in China edge and vision SoCs. The IP covers CNN through on-device GenAI use cases for consumer, automotive, and IoT customers.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-veri-silicon-1", "label": "VIP / NPU IP & design services", "url": "https://www.verisilicon.com/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "cerebras", "display_name": "Cerebras — wafer-scale engine", "category": "Startups", "directory_anchor": "Cerebras", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Cerebras_logo.png", "summary": "Cerebras builds wafer-scale AI processors (WSE) that place an enormous on-wafer SRAM/compute fabric into CS systems, avoiding many multi-GPU communication bottlenecks. WSE-1/2 established the approach; WSE-3 (2024, 5nm) powers CS-3 for foundation-model training and high-throughput inference with cloud and on-prem deployments.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [ { "id": "wse2", "name": "Cerebras Wafer Scale Engine 2 (WSE-2)", "product_type": "asic", "architecture": "Wafer-scale mesh of compute cores and on-chip SRAM", "generation": "WSE-2", "family": "Cerebras WSE", "market_segment": "Wafer-scale AI training and inference", "availability": "shipping", "form_factor": "Wafer-scale processor", "claim_ids": [ "wse2-core-count", "wse2-sram-capacity", "wse2-memory-bandwidth", "wse2-fabric-bandwidth" ], "compatibility_platform_ids": [ "cerebras-wse" ] }, { "id": "wse3", "name": "Cerebras Wafer Scale Engine 3 (WSE-3)", "product_type": "asic", "architecture": "5nm wafer-scale engine", "generation": "WSE-3", "family": "Cerebras WSE", "process_node": "5nm", "market_segment": "Wafer-scale foundation-model training and inference", "availability": "shipping", "form_factor": "Wafer-scale processor", "announced_at": "2024-03-13", "claim_ids": [ "wse3-core-count", "wse3-sram-capacity", "wse3-memory-bandwidth", "wse3-peak-ai-compute" ], "compatibility_platform_ids": [ "cerebras-wse" ] }, { "id": "wse3-turbo", "name": "Cerebras Wafer-Scale Engine 3 Turbo (WSE-3T)", "product_type": "asic", "architecture": "Wafer-scale processor with 900,000 AI-optimized cores", "generation": "WSE-3 Turbo", "family": "Cerebras WSE", "market_segment": "Large-scale AI training and inference", "availability": "announced", "form_factor": "46,225 mm² wafer-scale processor", "claim_ids": [ "wse3t-core-count", "wse3t-transistor-count", "wse3t-compute" ], "related_product_ids": [ "cs4-system" ] }, { "id": "cs4-system", "name": "Cerebras CS-4", "product_type": "system", "architecture": "Three WSE-3 Turbo processors with wafer links and Nexus platform", "generation": "CS-4", "family": "Cerebras CS", "market_segment": "Rack-scale AI inference", "availability": "announced", "form_factor": "Rack-scale AI accelerator system", "system_configuration": "Three WSE-3 Turbo processors per CS-4 system", "claim_ids": [ "cs4-wse-count" ], "related_product_ids": [ "wse3-turbo" ], "compatibility_platform_ids": [ "cerebras-wse" ] } ], "claims": [ { "id": "wse2-core-count", "subject_type": "product", "subject_id": "wse2", "topic": "architecture", "statement": "Cerebras specifies 850,000 cores in WSE-2.", "value": 850000, "unit": "cores", "scope": "Entire WSE-2 wafer-scale processor.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "system_configuration" }, "claim_status": "vendor_reported", "evidence_ids": [ "cerebras-wse2-whitepaper" ], "last_reviewed": "2026-11-05" }, { "id": "wse2-sram-capacity", "subject_type": "product", "subject_id": "wse2", "topic": "memory_capacity", "statement": "Cerebras specifies 40 GB of on-chip SRAM in WSE-2.", "value": 40, "unit": "GB SRAM", "scope": "On-chip SRAM across the WSE-2 processor.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "cerebras-wse2-whitepaper" ], "last_reviewed": "2026-11-05" }, { "id": "wse2-memory-bandwidth", "subject_type": "product", "subject_id": "wse2", "topic": "memory_bandwidth", "statement": "Cerebras specifies 20 PB/s on-chip memory bandwidth for WSE-2.", "value": 20, "unit": "PB/s", "scope": "Aggregate on-wafer memory bandwidth.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory", "directionality": "aggregate" }, "claim_status": "vendor_reported", "evidence_ids": [ "cerebras-wse2-whitepaper" ], "last_reviewed": "2026-11-05" }, { "id": "wse2-fabric-bandwidth", "subject_type": "product", "subject_id": "wse2", "topic": "interconnect", "statement": "Cerebras specifies 220 Pbit/s fabric bandwidth for WSE-2.", "value": 220, "unit": "Pbit/s", "scope": "Aggregate on-wafer fabric bandwidth.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "interconnect", "directionality": "aggregate" }, "claim_status": "vendor_reported", "evidence_ids": [ "cerebras-wse2-whitepaper" ], "last_reviewed": "2026-11-05" }, { "id": "wse3-core-count", "subject_type": "product", "subject_id": "wse3", "topic": "architecture", "statement": "Cerebras specifies 900,000 AI-optimized compute cores in WSE-3.", "value": 900000, "unit": "AI cores", "scope": "Entire WSE-3 wafer-scale processor.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "system_configuration" }, "claim_status": "vendor_reported", "evidence_ids": [ "cerebras-wse3-release" ], "last_reviewed": "2026-11-05" }, { "id": "wse3-sram-capacity", "subject_type": "product", "subject_id": "wse3", "topic": "memory_capacity", "statement": "Cerebras specifies 44 GB of on-chip SRAM in WSE-3.", "value": 44, "unit": "GB SRAM", "scope": "On-chip SRAM across the WSE-3 processor.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" }, "claim_status": "vendor_reported", "evidence_ids": [ "cerebras-wse3-release" ], "last_reviewed": "2026-11-05" }, { "id": "wse3-memory-bandwidth", "subject_type": "product", "subject_id": "wse3", "topic": "memory_bandwidth", "statement": "Cerebras reports 21 PB/s on-chip memory bandwidth for WSE-3.", "value": 21, "unit": "PB/s", "scope": "Aggregate on-wafer memory bandwidth.", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory", "directionality": "aggregate" }, "claim_status": "vendor_reported", "evidence_ids": [ "cerebras-wse3-sec-filing" ], "last_reviewed": "2026-11-05", "notes": "Issuer-reported figure in an SEC filing; not independently benchmarked." }, { "id": "wse3-peak-ai-compute", "subject_type": "product", "subject_id": "wse3", "topic": "compute", "statement": "Cerebras specifies 125 PFLOPs peak AI performance for WSE-3.", "value": 125, "unit": "PFLOPs peak AI performance", "scope": "WSE-3 processor; the source does not state a directly comparable precision in this summary figure.", "metric_context": { "metric_type": "theoretical_peak", "measurement_scope": "chip", "operation": "matrix", "precision": "unspecified", "sparsity": "unspecified" }, "claim_status": "vendor_reported", "evidence_ids": [ "cerebras-wse3-release" ], "last_reviewed": "2026-11-05", "notes": "Precision and operation mix are not specified in the announcement; do not compare directly with precision-specific GPU/ASIC FLOPs." }, { "id": "wse3t-core-count", "subject_type": "product", "subject_id": "wse3-turbo", "topic": "architecture", "statement": "Cerebras specifies 900,000 AI-optimized cores in WSE-3 Turbo.", "value": 900000, "unit": "AI-optimized cores", "scope": "Entire WSE-3 Turbo wafer-scale processor.", "claim_status": "vendor_reported", "evidence_ids": [ "cerebras-wse3t-2026" ], "last_reviewed": "2026-11-06" }, { "id": "wse3t-transistor-count", "subject_type": "product", "subject_id": "wse3-turbo", "topic": "architecture", "statement": "Cerebras specifies 4 trillion transistors in WSE-3 Turbo.", "value": 4, "unit": "trillion transistors", "scope": "Entire WSE-3 Turbo wafer-scale processor.", "claim_status": "vendor_reported", "evidence_ids": [ "cerebras-wse3t-2026" ], "last_reviewed": "2026-11-06" }, { "id": "wse3t-compute", "subject_type": "product", "subject_id": "wse3-turbo", "topic": "compute", "statement": "Cerebras advertises 250 PFLOPS AI compute for WSE-3 Turbo; the public product page does not specify a precision in this headline figure.", "value": 250, "unit": "PFLOPS AI compute", "scope": "Entire WSE-3 Turbo wafer-scale processor; precision and sparsity are not specified in the headline figure.", "claim_status": "vendor_reported", "evidence_ids": [ "cerebras-wse3t-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "theoretical_peak", "measurement_scope": "chip", "operation": "matrix", "precision": "unspecified", "sparsity": "unspecified" } }, { "id": "cs4-wse-count", "subject_type": "product", "subject_id": "cs4-system", "topic": "system_scale", "statement": "Cerebras says CS-4 combines three WSE-3 Turbo processors.", "value": 3, "unit": "WSE-3T processors", "scope": "Per CS-4 rack-scale system.", "claim_status": "vendor_reported", "evidence_ids": [ "cerebras-wse3t-2026" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "system", "operation": "system_configuration" } } ], "evidence": [ { "id": "cerebras-wse2-whitepaper", "title": "Cerebras CS-2 Whitepaper — WSE-2 architecture", "url": "https://cerebras.ai/wp-content/uploads/2021/04/Cerebras-CS-2-Whitepaper.pdf", "publisher": "Cerebras", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-05", "review_status": "reviewed", "notes": "Official Cerebras white paper. WSE-2 figures describe the wafer-scale processor, not a conventional packaged GPU or server." }, { "id": "cerebras-wse3-release", "title": "Cerebras announces third-generation Wafer-Scale Engine", "url": "https://www.cerebras.ai/press-release/cerebras-announces-third-generation-wafer-scale-engine", "publisher": "Cerebras", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2024-03-13", "checked_at": "2026-11-05", "review_status": "reviewed", "notes": "Official Cerebras announcement. The source lists 4 trillion transistors, 900,000 AI cores, 125 PFLOPs peak AI performance and 44 GB on-chip SRAM." }, { "id": "cerebras-wse3-sec-filing", "title": "Cerebras Systems SEC filing — WSE-3 architecture description", "url": "https://www.sec.gov/Archives/edgar/data/2021728/000162828026025762/cerebras-sx1april2026.htm", "publisher": "U.S. Securities and Exchange Commission (issuer filing)", "source_type": "government_or_regulatory", "independence": "official", "published_at": null, "checked_at": "2026-11-05", "review_status": "reviewed", "notes": "Cerebras issuer-filed SEC document. The 21 PB/s memory-bandwidth figure is issuer-reported in a regulatory filing, not an independent benchmark." }, { "id": "cerebras-wse3t-2026", "title": "Cerebras WSE-3 Turbo and CS-4 product information", "url": "https://www.cerebras.ai/chip", "publisher": "Cerebras", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official Cerebras product page. WSE-3T is the processor; CS-4 is a system with three WSE-3T processors. Headline compute figure lacks precision context." } ], "references": [ { "id": "ref-cerebras-1", "label": "Cerebras IPO (CBRS)", "url": "https://www.cnbc.com/2026/05/16/cerebras-blockbuster-ipo-boosts-hype-for-spacex-openai-anthropic.html", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-cerebras-2", "label": "OpenAI multi-year capacity deal", "url": "https://www.cnbc.com/2026/04/17/cerebras-new-ipo-ai-chips.html", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-cerebras-wse3t-cs4", "label": "WSE-3 Turbo / CS-4 product information", "url": "https://www.cerebras.ai/chip", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": null, "checked_at": "2026-11-06", "notes": "Reviewed against official Cerebras product page; compute figure retained without inferred precision." } ] }, { "id": "graphcore", "display_name": "Graphcore — IPU", "category": "Acquired / Legacy", "directory_anchor": "Graphcore", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Graphcore_logo.png", "summary": "Graphcore pioneered Intelligence Processing Units (IPU) with fine-grained MIMD parallelism and large on-chip memory (Colossus Mk1/Mk2, Bow). SoftBank acquired the company in July 2024; Graphcore remains a wholly owned, operating subsidiary and continues to use the Graphcore brand. It is tracked as part of SoftBank's portfolio, not as an independent startup.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [], "claims": [ { "id": "graphcore-softbank-ownership", "subject_type": "company", "subject_id": "graphcore", "topic": "availability", "statement": "Graphcore became a wholly owned SoftBank subsidiary in July 2024 and continues operating under the Graphcore name.", "scope": "Corporate ownership and operating status; reviewed 2026-11-06.", "claim_status": "source_confirmed", "evidence_ids": [ "graphcore-softbank-acquisition" ], "last_reviewed": "2026-11-06" } ], "evidence": [ { "id": "graphcore-softbank-acquisition", "title": "Graphcore joins SoftBank Group to build next generation of AI compute", "url": "https://www.graphcore.ai/posts/graphcore-joins-softbank-group-to-build-next-generation-of-ai-compute", "publisher": "Graphcore", "source_type": "company_primary", "independence": "vendor", "published_at": "2024-07-11", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Graphcore's official announcement says it was acquired by SoftBank, became a wholly owned subsidiary and would continue operating under the Graphcore name." } ], "references": [ { "id": "ref-graphcore-acquisition", "label": "Graphcore acquisition by SoftBank (completed)", "url": "https://www.graphcore.ai/posts/graphcore-joins-softbank-group-to-build-next-generation-of-ai-compute", "source_type": "company_primary", "review_status": "reviewed", "published_at": "2024-07-11", "checked_at": "2026-11-06", "notes": "Graphcore's official announcement says it was acquired by SoftBank, became a wholly owned subsidiary and would continue operating under the Graphcore name." } ], "corporate_status": { "ownership_status": "wholly_owned_subsidiary", "operating_status": "active", "parent_company": "SoftBank Group", "effective_date": "2024-07-11", "transaction_type": "acquisition", "notes": "Wholly owned by SoftBank; continues to operate under the Graphcore name. This is an ownership change, not a shutdown.", "evidence_ids": [ "graphcore-softbank-acquisition" ] } }, { "id": "tenstorrent", "display_name": "Tenstorrent — Wormhole / Blackhole", "category": "Startups", "directory_anchor": "Tenstorrent", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Tenstorrent_logo.png", "summary": "Tenstorrent's Blackhole p150b is documented with card- and chip-level boundaries. Galaxy Blackhole system availability is tracked separately from processor/card specification.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [ { "id": "tenstorrent-blackhole-p150b", "name": "Tenstorrent Blackhole p150b", "product_type": "asic", "architecture": "Tensix manycore processor with integrated RISC-V control cores and GDDR6", "generation": "Blackhole", "family": "Tenstorrent Blackhole", "process_node": "6nm", "market_segment": "Developer cards and scalable AI inference systems", "availability": "shipping", "form_factor": "PCIe add-in card, passive-cooled", "announced_at": "2025-04-03", "claim_ids": [ "blackhole-tensix-cores", "blackhole-riscv-cores", "blackhole-sram", "blackhole-memory", "blackhole-memory-bandwidth", "blackhole-fp8-compute", "blackhole-board-power" ], "availability_history": [ { "status": "announced", "effective_at": "2025-04-03", "evidence_id": "tenstorrent-blackhole-launch", "notes": "Blackhole cards launched and became available to order." }, { "status": "shipping", "effective_at": "2026-05-04", "evidence_id": "tenstorrent-galaxy-production", "notes": "Galaxy Blackhole entered production and volume shipping." } ] } ], "claims": [ { "id": "blackhole-tensix-cores", "subject_type": "product", "subject_id": "tenstorrent-blackhole-p150b", "topic": "architecture", "statement": "The Blackhole processor contains 120 Tensix cores.", "value": 120, "unit": "cores", "scope": "Per Blackhole processor.", "claim_status": "vendor_reported", "evidence_ids": [ "tenstorrent-blackhole-specs" ], "last_reviewed": "2026-11-06" }, { "id": "blackhole-riscv-cores", "subject_type": "product", "subject_id": "tenstorrent-blackhole-p150b", "topic": "architecture", "statement": "The Blackhole processor integrates 16 SiFive x280 RISC-V cores.", "value": 16, "unit": "RISC-V cores", "scope": "Per Blackhole processor.", "claim_status": "vendor_reported", "evidence_ids": [ "tenstorrent-blackhole-specs" ], "last_reviewed": "2026-11-06" }, { "id": "blackhole-sram", "subject_type": "product", "subject_id": "tenstorrent-blackhole-p150b", "topic": "memory_capacity", "statement": "The Blackhole processor integrates 180 MB SRAM.", "value": 180, "unit": "MB SRAM", "scope": "On-chip SRAM per processor.", "claim_status": "vendor_reported", "evidence_ids": [ "tenstorrent-blackhole-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" } }, { "id": "blackhole-memory", "subject_type": "product", "subject_id": "tenstorrent-blackhole-p150b", "topic": "memory_capacity", "statement": "The p150b card provides up to 32 GB GDDR6.", "value": 32, "unit": "GB GDDR6", "scope": "Per p150b card.", "claim_status": "vendor_reported", "evidence_ids": [ "tenstorrent-blackhole-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "board", "operation": "memory" } }, { "id": "blackhole-memory-bandwidth", "subject_type": "product", "subject_id": "tenstorrent-blackhole-p150b", "topic": "memory_bandwidth", "statement": "The p150b card provides 512 GB/s memory bandwidth.", "value": 512, "unit": "GB/s", "scope": "Per p150b card; vendor specification.", "claim_status": "vendor_reported", "evidence_ids": [ "tenstorrent-blackhole-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "board", "operation": "memory" } }, { "id": "blackhole-fp8-compute", "subject_type": "product", "subject_id": "tenstorrent-blackhole-p150b", "topic": "compute", "statement": "Tenstorrent lists 664 TFLOPS at BLOCKFP8 for the Blackhole card.", "value": 664, "unit": "TFLOPS BLOCKFP8", "scope": "Per p150b card; BLOCKFP8 vendor-defined format, not assumed equivalent to IEEE FP8.", "claim_status": "vendor_reported", "evidence_ids": [ "tenstorrent-blackhole-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "board", "operation": "matrix", "precision": "mixed", "sparsity": "unspecified" }, "notes": "BLOCKFP8 is retained verbatim and is not normalized to standard FP8." }, { "id": "blackhole-board-power", "subject_type": "product", "subject_id": "tenstorrent-blackhole-p150b", "topic": "power", "statement": "The p150b card has a 300 W total board power specification.", "value": 300, "unit": "W TBP", "scope": "Per p150b card.", "claim_status": "vendor_reported", "evidence_ids": [ "tenstorrent-blackhole-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "board", "operation": "power" } } ], "evidence": [ { "id": "tenstorrent-blackhole-specs", "title": "Blackhole PCIe Cards — specifications", "url": "https://docs.tenstorrent.com/aibs/blackhole/", "publisher": "Tenstorrent", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official hardware documentation. BLOCKFP8 is retained as vendor-defined precision." }, { "id": "tenstorrent-blackhole-launch", "title": "Tenstorrent launches Blackhole developer products", "url": "https://tenstorrent.com/en/newsroom/tenstorrent-launches-blackhole-developer-products-at-tenstorrent-dev-day", "publisher": "Tenstorrent", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2025-04-03", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official launch announcement dated 2025-04-03." }, { "id": "tenstorrent-galaxy-production", "title": "TT-Deploy: Galaxy Blackhole in production and shipping", "url": "https://tenstorrent.com/newsroom/tt-deploy", "publisher": "Tenstorrent", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2026-05-04", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official May 2026 update: Galaxy Blackhole production and volume shipping; system-level evidence, not a separate chip specification." } ], "references": [ { "id": "ref-tenstorrent-1", "label": "Galaxy Blackhole general availability", "url": "https://tenstorrent.com/en/newsroom/tenstorrent-enables-ai-at-scale-with-industry-leading-performance", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-tenstorrent-2", "label": "TT-Deploy production shipping", "url": "https://tenstorrent.com/en/newsroom/tt-deploy", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-tenstorrent-blackhole-specs", "label": "Blackhole PCIe Cards specification", "url": "https://docs.tenstorrent.com/aibs/blackhole/", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": null, "checked_at": "2026-11-06", "notes": "Board and processor specifications." }, { "id": "ref-tenstorrent-galaxy-production", "label": "TT-Deploy production update", "url": "https://tenstorrent.com/newsroom/tt-deploy", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": "2026-05-04", "checked_at": "2026-11-06", "notes": "Confirms Galaxy Blackhole production and volume shipping." } ] }, { "id": "etched", "display_name": "Etched — transformer ASICs", "category": "Startups", "directory_anchor": "Etched", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Etched_logo.png", "summary": "Etched's Sohu is a transformer-specialized inference ASIC delivered as a rack-scale system. Public sources support process-node and first-rack milestones, but not a full public chip datasheet; unsupported compute and memory figures are omitted.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [ { "id": "etched-sohu", "name": "Etched Sohu Transformer Inference ASIC", "product_type": "asic", "architecture": "Transformer-specialized inference ASIC; rack-level co-design with proprietary low-voltage inference and shared memory fabric", "generation": "Sohu", "family": "Etched Sohu", "process_node": "TSMC N4P", "market_segment": "Transformer inference and frontier inference clusters", "availability": "shipping", "form_factor": "Rack-scale inference system", "claim_ids": [ "etched-sohu-a0", "etched-sohu-first-rack" ], "availability_history": [ { "status": "announced", "effective_at": "2026-06-30", "evidence_id": "etched-sohu-cluster", "notes": "Etched disclosed A0 silicon and rack-scale customer validation." }, { "status": "shipping", "effective_at": "2026-08-18", "evidence_id": "etched-sohu-first-rack", "notes": "Etched announced first rack shipment to Jane Street." } ] } ], "claims": [ { "id": "etched-sohu-a0", "subject_type": "product", "subject_id": "etched-sohu", "topic": "process_node", "statement": "Etched reports that its Sohu A0 silicon returned from TSMC N4P.", "scope": "Company-reported first-silicon milestone; not a public production datasheet.", "claim_status": "vendor_reported", "evidence_ids": [ "etched-sohu-cluster" ], "last_reviewed": "2026-11-06" }, { "id": "etched-sohu-first-rack", "subject_type": "product", "subject_id": "etched-sohu", "topic": "deployment", "statement": "Etched announced shipment of its first rack to Jane Street.", "scope": "First customer rack shipment; does not disclose production volume or independent benchmark results.", "claim_status": "vendor_reported", "evidence_ids": [ "etched-sohu-first-rack" ], "last_reviewed": "2026-11-06" } ], "evidence": [ { "id": "etched-sohu-cluster", "title": "Frontier Inference Clusters", "url": "https://www.etched.com/progress/frontier-inference-clusters", "publisher": "Etched", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2026-06-30", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official company update dated 2026-06-30. Describes A0 silicon, TSMC N4P and customer rack validation; detailed chip specifications not publicly disclosed." }, { "id": "etched-sohu-first-rack", "title": "From Zero to One", "url": "https://www.etched.com/progress/from-zero-to-one", "publisher": "Etched", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2026-08-18", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official company update dated 2026-08-18 announcing first rack shipment to Jane Street; not an independent performance validation." } ], "references": [ { "id": "ref-etched-1", "label": "Etched hits $5B valuation", "url": "https://techcrunch.com/2026/06/30/nvidia-competitor-etched-hits-5b-valuation-1b-in-sales-for-ai-chip/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-etched-sohu-cluster", "label": "Etched Frontier Inference Clusters", "url": "https://www.etched.com/progress/frontier-inference-clusters", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": "2026-06-30", "checked_at": "2026-11-06", "notes": "Architecture and A0 milestone; numerical product specifications not publicly disclosed." }, { "id": "ref-etched-sohu-first-rack", "label": "Etched first Sohu rack shipment", "url": "https://www.etched.com/progress/from-zero-to-one", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": "2026-08-18", "checked_at": "2026-11-06", "notes": "Company announcement of first rack shipment to Jane Street." } ] }, { "id": "groq", "display_name": "Groq — LPU", "category": "Startups", "directory_anchor": "Groq", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Groq_logo.png", "summary": "Groq’s Language Processing Unit (LPU) uses a deterministic, compiler-scheduled architecture for ultra-low-latency LLM token generation. After building a cloud inference service on LPU racks, Groq’s technology was licensed by NVIDIA (late 2025), with key talent joining NVIDIA; GTC 2026 described LPU-class engines inside the Vera Rubin AI factory for efficient decode alongside Rubin GPUs.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [], "claims": [ { "id": "groq-independent-after-nvidia-license", "subject_type": "company", "subject_id": "groq", "topic": "availability", "statement": "Groq states it remains independent after a non-exclusive technology licensing agreement with NVIDIA and selected team hires.", "scope": "Corporate ownership and operating status; reviewed 2026-11-06.", "claim_status": "vendor_reported", "evidence_ids": [ "groq-nvidia-license-not-acquisition", "groq-2026-growth-capital" ], "last_reviewed": "2026-11-06" } ], "evidence": [ { "id": "groq-nvidia-license-not-acquisition", "title": "Groq and NVIDIA enter non-exclusive inference technology licensing agreement", "url": "https://groq.com/newsroom/groq-and-nvidia-enter-non-exclusive-inference-technology-licensing-agreement-to-accelerate-ai-inference-at-global-scale", "publisher": "Groq", "source_type": "company_primary", "independence": "vendor", "published_at": "2025-12-24", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Groq states the agreement is non-exclusive, selected leaders and team members joined NVIDIA, and Groq continues as an independent company with GroqCloud operating." }, { "id": "groq-2026-growth-capital", "title": "Groq raises $650M to scale its AI inference cloud business", "url": "https://groq.com/newsroom/groq-raises-usd650m-to-scale-its-ai-inference-cloud-business", "publisher": "Groq", "source_type": "company_primary", "independence": "vendor", "published_at": "2026-06-22", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Groq announced $650M growth capital and continued independent operation of its inference cloud after the NVIDIA licensing agreement." } ], "references": [ { "id": "ref-groq-1", "label": "NVIDIA Vera Rubin includes Groq LPU", "url": "https://investor.nvidia.com/news/press-release-details/2026/NVIDIA-Vera-Rubin-Opens-Agentic-AI-Frontier/default.aspx", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-groq-nvidia-license", "label": "NVIDIA non-exclusive technology license (not an acquisition)", "url": "https://groq.com/newsroom/groq-and-nvidia-enter-non-exclusive-inference-technology-licensing-agreement-to-accelerate-ai-inference-at-global-scale", "source_type": "company_primary", "review_status": "reviewed", "published_at": "2025-12-24", "checked_at": "2026-11-06", "notes": "Groq states the agreement is non-exclusive, selected leaders and team members joined NVIDIA, and Groq continues as an independent company with GroqCloud operating." }, { "id": "ref-groq-2026-independent-cloud", "label": "Groq 2026 growth financing and inference-cloud expansion", "url": "https://groq.com/newsroom/groq-raises-usd650m-to-scale-its-ai-inference-cloud-business", "source_type": "company_primary", "review_status": "reviewed", "published_at": "2026-06-22", "checked_at": "2026-11-06", "notes": "Groq announced $650M growth capital and continued independent operation of its inference cloud after the NVIDIA licensing agreement." } ], "corporate_status": { "ownership_status": "independent", "operating_status": "active", "effective_date": "2025-12-24", "transaction_type": "license_and_talent_hire", "notes": "Groq remains an independent company. NVIDIA licensed technology non-exclusively and hired selected leaders/team members; no equity, customer contracts or existing products were purchased in the licensing transaction.", "evidence_ids": [ "groq-nvidia-license-not-acquisition", "groq-2026-growth-capital" ] } }, { "id": "samba-nova", "display_name": "SambaNova — RDU", "category": "Startups", "directory_anchor": "SambaNova", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/SambaNova_logo.png", "summary": "SambaNova's SN50 is its fifth-generation RDU for memory-bound decode and agentic inference. Per-chip compute/memory specifications are separated from the system-level 256-RDU scale-up claim.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [ { "id": "sambanova-sn50-rdu", "name": "SambaNova SN50 Reconfigurable Dataflow Unit", "product_type": "asic", "architecture": "Fifth-generation Reconfigurable Dataflow Unit with dataflow execution and three-tier memory", "generation": "SN50 / fifth-generation RDU", "family": "SambaNova RDU", "process_node": "TSMC 5nm", "market_segment": "Agentic AI inference and decode", "availability": "announced", "form_factor": "RDU accelerator chip", "claim_ids": [ "sn50-bf16", "sn50-fp8", "sn50-sram", "sn50-hbm", "sn50-ddr", "sn50-scaleup" ], "availability_history": [ { "status": "announced", "effective_at": "2026-09-02", "evidence_id": "sambanova-sn50-product", "notes": "SN50 architecture and scaling described at Hot Chips 2026." }, { "status": "announced", "effective_at": "2026-11-03", "evidence_id": "sambanova-sn50-supermicro", "notes": "Supermicro announced plans for an initial 10,000 SN50 RDU chips; production availability is not inferred from the plan." } ] } ], "claims": [ { "id": "sn50-bf16", "subject_type": "product", "subject_id": "sambanova-sn50-rdu", "topic": "compute", "statement": "SambaNova lists 1,600 TFLOPS BF16 compute for SN50.", "value": 1600, "unit": "TFLOPS BF16", "scope": "Per RDU chip; vendor specification.", "claim_status": "vendor_reported", "evidence_ids": [ "sambanova-sn50-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "matrix", "precision": "BF16", "sparsity": "unspecified" } }, { "id": "sn50-fp8", "subject_type": "product", "subject_id": "sambanova-sn50-rdu", "topic": "compute", "statement": "SambaNova lists 3,200 TFLOPS FP8 compute for SN50.", "value": 3200, "unit": "TFLOPS FP8", "scope": "Per RDU chip; vendor specification.", "claim_status": "vendor_reported", "evidence_ids": [ "sambanova-sn50-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "matrix", "precision": "FP8", "sparsity": "unspecified" } }, { "id": "sn50-sram", "subject_type": "product", "subject_id": "sambanova-sn50-rdu", "topic": "memory_capacity", "statement": "SN50 integrates 432 MB on-chip SRAM.", "value": 432, "unit": "MB SRAM", "scope": "Per RDU chip.", "claim_status": "vendor_reported", "evidence_ids": [ "sambanova-sn50-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" } }, { "id": "sn50-hbm", "subject_type": "product", "subject_id": "sambanova-sn50-rdu", "topic": "memory_capacity", "statement": "SN50 integrates 64 GB HBM2E.", "value": 64, "unit": "GB HBM2E", "scope": "Per RDU chip.", "claim_status": "vendor_reported", "evidence_ids": [ "sambanova-sn50-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" } }, { "id": "sn50-ddr", "subject_type": "product", "subject_id": "sambanova-sn50-rdu", "topic": "memory_capacity", "statement": "SN50 supports up to 512 GB DDR5 in its three-tier memory architecture.", "value": 512, "unit": "GB DDR5 (up to)", "scope": "Per RDU chip / associated memory tier; vendor states up to 512 GB.", "claim_status": "vendor_reported", "evidence_ids": [ "sambanova-sn50-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" } }, { "id": "sn50-scaleup", "subject_type": "product", "subject_id": "sambanova-sn50-rdu", "topic": "system_scale", "statement": "SambaNova states SN50 systems can scale up to 256 RDUs.", "value": 256, "unit": "RDUs", "scope": "System scale-up limit; not per-chip capability.", "claim_status": "vendor_reported", "evidence_ids": [ "sambanova-sn50-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "system", "operation": "system_configuration" } } ], "evidence": [ { "id": "sambanova-sn50-specs", "title": "Reconfigurable Dataflow Unit (RDU) Chip — SN50 specifications", "url": "https://sambanova.ai/products/rdu-ai-chips", "publisher": "SambaNova", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official product page lists SN50 1,600 TFLOPS BF16, 3,200 TFLOPS FP8, 432 MB SRAM, 64 GB HBM2E, up to 512 GB DDR5, and scale-up to 256 RDUs." }, { "id": "sambanova-sn50-product", "title": "Hot Chips 2026: Dataflow at Scale", "url": "https://sambanova.ai/blog/hot-chips-2026-dataflow-at-scale", "publisher": "SambaNova", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2026-09-02", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official Hot Chips 2026 architecture presentation; complements current SN50 product specifications." }, { "id": "sambanova-sn50-supermicro", "title": "SambaNova SN50 Chips to Power Supermicro's New Inference Racks", "url": "https://sambanova.ai/press/sambanova-and-supermicro-partnership", "publisher": "SambaNova", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2026-11-03", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official announcement dated 2026-11-03; Supermicro initially plans for 10,000 SN50 chips. A planned order is not independently verified shipment." } ], "references": [ { "id": "ref-samba-nova-1", "label": "SN50 RDU, Intel collab, $350M+ Series E", "url": "https://sambanova.ai/press/sambanova-unveils-fastest-chip-for-agentic-ai-collaborates-with-intel-and-raises-350m", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-sambanova-sn50-specs", "label": "SN50 RDU product specifications", "url": "https://sambanova.ai/products/rdu-ai-chips", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": null, "checked_at": "2026-11-06", "notes": "Official chip specifications and memory tiers." }, { "id": "ref-sambanova-sn50-supermicro", "label": "Supermicro SN50 rack collaboration", "url": "https://sambanova.ai/press/sambanova-and-supermicro-partnership", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": "2026-11-03", "checked_at": "2026-11-06", "notes": "Announced initial plan for 10,000 chips; not a verified shipment record." } ] }, { "id": "mythic", "display_name": "Mythic — analog compute-in-memory", "category": "Startups", "directory_anchor": "Mythic", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Mythic_logo.png", "summary": "Mythic builds Analog Processing Units (APUs) that use flash-based compute-in-memory for energy-efficient inference at the edge and in data centers. After years of analog AI development, 2025–2026 funding and the Videantis acquisition add digital processor IP for a hybrid analog/digital platform aimed at robotics, automotive, and defense.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-mythic-1", "label": "$125M Series D", "url": "https://www.businesswire.com/news/home/20251217546249/en/Mythic-to-Challenge-AIs-GPU-Pantheon-with-100x-Energy-Advantage-and-Oversubscribed-%24125M-Raise", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-mythic-2", "label": "Acquires Videantis", "url": "https://mythic.ai/whats-new/mythic-acquires-videantis-one-of-europes-leading-digital-processor-ip-companies-to-build-the-worlds-most-energy-efficient-ai-compute-platform/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "hailo", "display_name": "Hailo — edge AI accelerators", "category": "Startups", "directory_anchor": "Hailo", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Hailo_logo.png", "summary": "Hailo designs high-efficiency edge AI accelerators for vision and, with Hailo-10, on-device generative AI. Hailo-8 established the structure-sparsity / efficient-NPU brand in smart cameras and industrial vision; Hailo-10H adds LLM/VLM-class GenAI at low watts with automotive qualification paths.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-hailo-1", "label": "Hailo-10H GA for edge GenAI", "url": "https://hailo.ai/company-overview/newsroom/news/hailo-announces-general-availability-of-hailo-10h-edge-ai-accelerator-with-generative-ai-capabilities/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "furiosa", "display_name": "FuriosaAI — RNGD / TCP", "category": "Startups", "directory_anchor": "Furiosa", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Furiosa_logo.png", "summary": "FuriosaAI's RNGD is a production-stage inference accelerator. Per-card metrics and the eight-card NXT server are represented separately to avoid mixing chip and system specifications.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [ { "id": "furiosa-rngd", "name": "FuriosaAI RNGD Tensor Contraction Processor", "product_type": "npu", "architecture": "Tensor Contraction Processor (TCP)", "generation": "Second-generation RNGD", "family": "FuriosaAI RNGD", "process_node": "TSMC 5nm", "market_segment": "Data-center LLM and multimodal inference", "availability": "production", "form_factor": "PCIe dual-slot accelerator card", "claim_ids": [ "rngd-fp8", "rngd-bf16", "rngd-hbm", "rngd-bandwidth", "rngd-power" ], "availability_history": [ { "status": "production", "effective_at": "2026-01", "evidence_id": "furiosa-rngd-production", "notes": "Furiosa says RNGD reached mass production in January 2026; exact day not stated." } ] }, { "id": "furiosa-nxt-rngd-server", "name": "FuriosaAI NXT RNGD Server", "product_type": "system", "architecture": "Eight RNGD TCP accelerators in a turnkey 4U server", "generation": "NXT RNGD Server", "family": "FuriosaAI RNGD", "market_segment": "On-premises and cloud inference", "availability": "unknown", "form_factor": "4U rackmount server", "system_configuration": "8 × RNGD cards; dual AMD EPYC 9354; 1 TB DDR5", "claim_ids": [ "nxt-rngd-fp8", "nxt-rngd-hbm", "nxt-rngd-power" ], "related_product_ids": [ "furiosa-rngd" ] } ], "claims": [ { "id": "rngd-fp8", "subject_type": "product", "subject_id": "furiosa-rngd", "topic": "compute", "statement": "Furiosa specifies 512 TFLOPS FP8 for RNGD.", "value": 512, "unit": "TFLOPS FP8", "scope": "Per RNGD accelerator chip/card; vendor specification.", "claim_status": "vendor_reported", "evidence_ids": [ "furiosa-rngd-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "matrix", "precision": "FP8", "sparsity": "unspecified" } }, { "id": "rngd-bf16", "subject_type": "product", "subject_id": "furiosa-rngd", "topic": "compute", "statement": "Furiosa specifies 256 TFLOPS BF16 for RNGD.", "value": 256, "unit": "TFLOPS BF16", "scope": "Per RNGD accelerator chip/card; vendor specification.", "claim_status": "vendor_reported", "evidence_ids": [ "furiosa-rngd-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "matrix", "precision": "BF16", "sparsity": "unspecified" } }, { "id": "rngd-hbm", "subject_type": "product", "subject_id": "furiosa-rngd", "topic": "memory_capacity", "statement": "RNGD integrates 48 GB HBM3.", "value": 48, "unit": "GB HBM3", "scope": "Per RNGD accelerator.", "claim_status": "vendor_reported", "evidence_ids": [ "furiosa-rngd-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" } }, { "id": "rngd-bandwidth", "subject_type": "product", "subject_id": "furiosa-rngd", "topic": "memory_bandwidth", "statement": "RNGD provides 1.5 TB/s HBM bandwidth.", "value": 1.5, "unit": "TB/s", "scope": "Per RNGD accelerator.", "claim_status": "vendor_reported", "evidence_ids": [ "furiosa-rngd-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" } }, { "id": "rngd-power", "subject_type": "product", "subject_id": "furiosa-rngd", "topic": "power", "statement": "Furiosa's current developer documentation lists 180 W TDP for RNGD.", "value": 180, "unit": "W TDP", "scope": "Per accelerator card; current 2026 developer documentation.", "claim_status": "vendor_reported", "evidence_ids": [ "furiosa-rngd-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "board", "operation": "power" } }, { "id": "nxt-rngd-fp8", "subject_type": "product", "subject_id": "furiosa-nxt-rngd-server", "topic": "compute", "statement": "NXT RNGD Server provides 4,096 TFLOPS FP8 across eight RNGD processors.", "value": 4096, "unit": "TFLOPS FP8", "scope": "Per 8-card 4U server; aggregate system figure.", "claim_status": "vendor_reported", "evidence_ids": [ "furiosa-nxt-server-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "server", "operation": "matrix", "precision": "FP8", "sparsity": "unspecified" } }, { "id": "nxt-rngd-hbm", "subject_type": "product", "subject_id": "furiosa-nxt-rngd-server", "topic": "memory_capacity", "statement": "NXT RNGD Server provides 384 GB HBM3 across eight cards.", "value": 384, "unit": "GB HBM3", "scope": "Aggregate across eight accelerators in one server.", "claim_status": "vendor_reported", "evidence_ids": [ "furiosa-nxt-server-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "server", "operation": "memory" } }, { "id": "nxt-rngd-power", "subject_type": "product", "subject_id": "furiosa-nxt-rngd-server", "topic": "power", "statement": "NXT RNGD Server system power usage is listed as 3,000 W.", "value": 3000, "unit": "W system power", "scope": "Per 4U server; system power, not card TDP.", "claim_status": "vendor_reported", "evidence_ids": [ "furiosa-nxt-server-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "server", "operation": "power" } } ], "evidence": [ { "id": "furiosa-rngd-specs", "title": "RNGD hardware specifications — 2026 developer documentation", "url": "https://developer.furiosa.ai/latest/en/overview/rngd.html", "publisher": "FuriosaAI", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official developer documentation: 5nm, 512 TFLOPS FP8, 256 TFLOPS BF16, 48GB HBM3, 1.5TB/s, 180W TDP." }, { "id": "furiosa-rngd-production", "title": "FuriosaAI closes $620 million Series D; RNGD in mass production", "url": "https://furiosa.ai/blog/furiosaai-620-million-series-d", "publisher": "FuriosaAI", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2026-10-28", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official update dated 2026-10-28. Company says RNGD reached mass production in January 2026; 20,000 cards planned for 2026. Volume figure is vendor plan, not independently audited shipment." }, { "id": "furiosa-nxt-server-specs", "title": "NXT RNGD Server specifications", "url": "https://furiosa.ai/rngd-server", "publisher": "FuriosaAI", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official turnkey server page: 8 accelerators, 4,096 TFLOPS FP8, 384GB HBM3 and 3,000W system power." } ], "references": [ { "id": "ref-furiosa-1", "label": "RNGD mass production", "url": "https://furiosa.ai/blog/rngd-enters-mass-production-the-high-performance-ai-accelerator-for-any-data-center", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-furiosa-2", "label": "Broadcom inference partnership", "url": "https://furiosa.ai/blog/furiosaai-partners-with-broadcom-to-build-next-generation-inference-platform-for-the-agentic-era", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-furiosa-rngd-specs", "label": "RNGD developer hardware specification", "url": "https://developer.furiosa.ai/latest/en/overview/rngd.html", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": null, "checked_at": "2026-11-06", "notes": "Per-accelerator chip/card specifications." }, { "id": "ref-furiosa-rngd-production", "label": "RNGD mass-production update", "url": "https://furiosa.ai/blog/furiosaai-620-million-series-d", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": "2026-10-28", "checked_at": "2026-11-06", "notes": "Company-reported mass-production status and 2026 production plan." }, { "id": "ref-furiosa-nxt-server", "label": "NXT RNGD Server", "url": "https://furiosa.ai/rngd-server", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": null, "checked_at": "2026-11-06", "notes": "System-level configuration and aggregate specifications." } ] }, { "id": "kinara", "display_name": "Kinara (ex–Deep Vision)", "category": "Acquired / Legacy", "directory_anchor": "Kinara", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Deepvision_logo.png", "summary": "Kinara developed Ara / Prisma edge NPUs for vision and on-device GenAI. NXP completed its acquisition on 27 October 2025; the technology and product lineage should now be tracked within NXP's edge-AI portfolio rather than as an independent startup.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [], "claims": [ { "id": "kinara-nxp-acquisition-completed-claim", "subject_type": "company", "subject_id": "kinara", "topic": "availability", "statement": "NXP completed the Kinara acquisition on 27 October 2025; Kinara is no longer an independent startup.", "scope": "Corporate ownership and operating status; reviewed 2026-11-06.", "claim_status": "source_confirmed", "evidence_ids": [ "kinara-nxp-acquisition-completed" ], "last_reviewed": "2026-11-06" } ], "evidence": [ { "id": "kinara-nxp-acquisition-completed", "title": "NXP completes acquisitions of Aviva Links and Kinara", "url": "https://investors.nxp.com/news-releases/news-release-details/nxp-completes-acquisitions-aviva-links-and-kinara-advance", "publisher": "NXP Semiconductors", "source_type": "company_primary", "independence": "vendor", "published_at": "2025-10-28", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "NXP states it closed the Kinara acquisition on 27 October 2025 for $307 million; Kinara's edge NPU portfolio complements NXP's Industrial & IoT and Automotive markets." } ], "references": [ { "id": "ref-kinara-acquisition-completed", "label": "NXP completes Kinara acquisition", "url": "https://investors.nxp.com/news-releases/news-release-details/nxp-completes-acquisitions-aviva-links-and-kinara-advance", "source_type": "company_primary", "review_status": "reviewed", "published_at": "2025-10-28", "checked_at": "2026-11-06", "notes": "NXP states it closed the Kinara acquisition on 27 October 2025 for $307 million; Kinara's edge NPU portfolio complements NXP's Industrial & IoT and Automotive markets." } ], "corporate_status": { "ownership_status": "acquired_business_unit", "operating_status": "active", "parent_company": "NXP Semiconductors", "effective_date": "2025-10-27", "transaction_type": "acquisition", "notes": "Acquisition completed. Track Kinara's Ara / Prisma technology as part of NXP's edge-AI portfolio; do not present Kinara as an independent startup.", "evidence_ids": [ "kinara-nxp-acquisition-completed" ] } }, { "id": "si-ma", "display_name": "SiMa.ai — Modalix MLSoC", "category": "Startups", "directory_anchor": "SiMa", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/SiMa_logo.png", "summary": "SiMa.ai builds MLSoC platforms for edge / Physical AI—robots, industrial, automotive, and vision—combining CPU, ML accelerator, and software (Palette / LLiMa) for CNN through Transformer/LLM workloads at low power. Modalix is the second-generation production platform after the first MLSoC.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-si-ma-1", "label": "Modalix platform in production", "url": "https://sima.ai/press-release/sima-ai-next-gen-platform-for-physical-ai-in-production/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "d-matrix", "display_name": "d-Matrix — Corsair", "category": "Startups", "directory_anchor": "d-matrix", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/d-matrix_logo.png", "summary": "d-Matrix Corsair is represented as a platform/system record because public evidence establishes platform production and its decode role, not a complete independently validated chip specification.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [ { "id": "dmatrix-corsair-platform", "name": "d-Matrix Corsair Inference Accelerator Platform", "product_type": "system", "architecture": "Digital in-memory compute accelerator platform for low-latency decode and heterogeneous disaggregated inference", "generation": "Corsair", "family": "d-Matrix Corsair", "market_segment": "Data-center LLM inference, especially decode", "availability": "production", "form_factor": "Rack-scale accelerator platform", "claim_ids": [ "corsair-full-production", "corsair-disaggregated-inference" ], "availability_history": [ { "status": "production", "effective_at": "2026-06-09", "evidence_id": "corsair-full-production", "notes": "d-Matrix announced Corsair entered full production." } ] } ], "claims": [ { "id": "corsair-full-production", "subject_type": "product", "subject_id": "dmatrix-corsair-platform", "topic": "availability", "statement": "d-Matrix announced that the Corsair inference accelerator platform entered full production.", "scope": "Platform-level status as announced by vendor on 2026-06-09; volume shipments were to begin for priority customers.", "claim_status": "vendor_reported", "evidence_ids": [ "corsair-full-production" ], "last_reviewed": "2026-11-06" }, { "id": "corsair-disaggregated-inference", "subject_type": "product", "subject_id": "dmatrix-corsair-platform", "topic": "architecture", "statement": "d-Matrix positions Corsair for decode in heterogeneous inference systems paired with GPUs for prefill.", "scope": "Vendor-described deployment model; not a universal workload-performance guarantee.", "claim_status": "vendor_reported", "evidence_ids": [ "corsair-full-production" ], "last_reviewed": "2026-11-06" } ], "evidence": [ { "id": "corsair-full-production", "title": "Corsair AI Inference Platform Enters Full Production", "url": "https://www.d-matrix.ai/announcements/d-matrix-corsair-ai-inference-platform-enters-full-production-to-meet-customer-demand/", "publisher": "d-Matrix", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2026-06-09", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official announcement dated 2026-06-09. Describes full production and planned volume shipments; no detailed chip specification in this announcement." } ], "references": [ { "id": "ref-d-matrix-1", "label": "Corsair enters full production", "url": "https://www.d-matrix.ai/announcements/d-matrix-corsair-ai-inference-platform-enters-full-production-to-meet-customer-demand/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-d-matrix-2", "label": "Series C / $2B valuation", "url": "https://cryptobriefing.com/d-matrix-corsair-challenges-nvidia-ai-inference/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "blaize", "display_name": "Blaize — Graph Streaming Processor", "category": "Startups", "directory_anchor": "Blaize", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Blaize_logo.png", "summary": "Blaize’s Graph Streaming Processor (GSP) targets graph-native edge AI for vision and GenAI in industrial and smart-city deployments. After years as a private edge-AI vendor, Blaize listed via SPAC (Nasdaq: BZAI) in 2025 to scale product and go-to-market.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-blaize-1", "label": "Blaize AI edge platforms", "url": "https://www.blaize.com/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "syn-sense", "display_name": "SynSense (ex–aiCTX)", "category": "Startups", "directory_anchor": "SynSense", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/aiCTX_logo.png", "summary": "SynSense (formerly aiCTX) builds neuromorphic and event-based sensing+compute chips (Speck, Xylo) for ultra-low-power always-on perception. Collaborations such as with iniVation extend event-camera + neuromorphic pipelines for edge AI.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-syn-sense-1", "label": "SynSense neuromorphic products", "url": "https://www.synsense.ai/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "sagence", "display_name": "Sagence AI (ex–Analog Inference)", "category": "Startups", "directory_anchor": "Sagence", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/AnalogInference_logo.png", "summary": "Sagence AI (rebranded from Analog Inference in Nov 2024) develops analog compute-in-memory accelerators aimed at energy-efficient LLM and vision inference for datacenter and edge deployments—part of the broader analog-AI cohort seeking orders-of-magnitude efficiency vs. digital GPUs on inference.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-sagence-1", "label": "Sagence AI analog CIM", "url": "https://www.sagence.ai/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "huawei-ascend", "display_name": "Huawei Ascend / HiSilicon", "category": "China AI Accelerator Vendors", "directory_anchor": "HuaweiAscend", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/HiSilicon_logo.png", "summary": "Huawei Ascend 950PR and 950DT are separately represented by their different memory configurations and target phases. The family-level 2026 commercial-deployment statement is qualified and is not treated as independent verification of each card SKU.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [ { "id": "ascend-950pr", "name": "Huawei Ascend 950PR", "product_type": "npu", "architecture": "SIMD/SIMT; HiBL 1.0 memory variant; Prefill and recommendation oriented", "generation": "Ascend 950", "family": "Huawei Ascend 950", "market_segment": "AI prefill and recommendation", "availability": "announced", "form_factor": "Accelerator card / supernode server", "claim_ids": [ "ascend950pr-fp8", "ascend950pr-interconnect", "ascend950pr-positioning" ], "availability_history": [ { "status": "announced", "effective_at": "2025-09-18", "evidence_id": "huawei-ascend-roadmap", "notes": "Huawei announced the 950PR roadmap and planned Q1 2026 introduction; no distinct 950PR shipment evidence is used here." } ], "compatibility_platform_ids": [ "huawei-ascend" ] }, { "id": "ascend-950dt", "name": "Huawei Ascend 950DT", "product_type": "npu", "architecture": "SIMD/SIMT; HiZQ 2.0 HBM variant; Decode and training oriented", "generation": "Ascend 950", "family": "Huawei Ascend 950", "market_segment": "AI decode and training", "availability": "shipping", "form_factor": "Accelerator card / Atlas 950 supernode", "claim_ids": [ "ascend950dt-memory", "ascend950dt-bandwidth", "ascend950dt-interconnect", "ascend950dt-positioning" ], "availability_history": [ { "status": "announced", "effective_at": "2025-09-18", "evidence_id": "huawei-ascend-roadmap", "notes": "Huawei announced Ascend 950DT roadmap and planned Q4 2026 introduction." }, { "status": "shipping", "effective_at": "2026-09", "evidence_id": "huawei-ascend-2026", "notes": "Huawei stated Ascend 950 supernodes had entered commercial scale; family-level evidence, not independent verification of each card SKU." } ], "compatibility_platform_ids": [ "huawei-ascend" ] } ], "claims": [ { "id": "ascend950pr-fp8", "subject_type": "product", "subject_id": "ascend-950pr", "topic": "compute", "statement": "Huawei lists 1 PFLOPS FP8 compute for the Ascend 950 series, including 950PR.", "value": 1, "unit": "PFLOPS FP8", "scope": "Per Ascend 950 die; vendor roadmap figure, not an independent benchmark.", "claim_status": "vendor_reported", "evidence_ids": [ "huawei-ascend-roadmap" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "matrix", "precision": "FP8", "sparsity": "unspecified" } }, { "id": "ascend950pr-interconnect", "subject_type": "product", "subject_id": "ascend-950pr", "topic": "interconnect", "statement": "Huawei specifies 2 TB/s interconnect bandwidth for the Ascend 950 series.", "value": 2, "unit": "TB/s", "scope": "Per accelerator; keynote summary does not fully detail directionality.", "claim_status": "vendor_reported", "evidence_ids": [ "huawei-ascend-roadmap" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "interconnect" } }, { "id": "ascend950pr-positioning", "subject_type": "product", "subject_id": "ascend-950pr", "topic": "architecture", "statement": "Huawei positions Ascend 950PR for inference Prefill and recommendation workloads, using HiBL 1.0.", "scope": "Vendor architecture positioning; workload fit is not independently benchmarked.", "claim_status": "vendor_reported", "evidence_ids": [ "huawei-ascend-roadmap" ], "last_reviewed": "2026-11-06" }, { "id": "ascend950dt-memory", "subject_type": "product", "subject_id": "ascend-950dt", "topic": "memory_capacity", "statement": "Huawei specifies 144 GB HiZQ 2.0 memory for Ascend 950DT.", "value": 144, "unit": "GB HiZQ 2.0", "scope": "Per accelerator chip; vendor specification.", "claim_status": "vendor_reported", "evidence_ids": [ "huawei-ascend-roadmap" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" } }, { "id": "ascend950dt-bandwidth", "subject_type": "product", "subject_id": "ascend-950dt", "topic": "memory_bandwidth", "statement": "Huawei specifies 4 TB/s memory bandwidth for Ascend 950DT.", "value": 4, "unit": "TB/s", "scope": "Per accelerator chip; vendor specification.", "claim_status": "vendor_reported", "evidence_ids": [ "huawei-ascend-roadmap" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" } }, { "id": "ascend950dt-interconnect", "subject_type": "product", "subject_id": "ascend-950dt", "topic": "interconnect", "statement": "Huawei specifies 2 TB/s interconnect bandwidth for Ascend 950DT.", "value": 2, "unit": "TB/s", "scope": "Per accelerator; vendor keynote summary figure.", "claim_status": "vendor_reported", "evidence_ids": [ "huawei-ascend-roadmap" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "interconnect" } }, { "id": "ascend950dt-positioning", "subject_type": "product", "subject_id": "ascend-950dt", "topic": "architecture", "statement": "Huawei positions Ascend 950DT for inference Decode and training workloads, using HiZQ 2.0.", "scope": "Vendor architecture positioning; workload fit is not independently benchmarked.", "claim_status": "vendor_reported", "evidence_ids": [ "huawei-ascend-roadmap" ], "last_reviewed": "2026-11-06" } ], "evidence": [ { "id": "huawei-ascend-roadmap", "title": "Huawei Connect 2025 keynote: Ascend roadmap and Atlas 950", "url": "https://www.huawei.com/cn/news/2025/9/hc-xu-keynote-speech", "publisher": "Huawei", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2025-09-18", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official keynote dated 2025-09-18. Lists 950PR/DT architecture, memory, bandwidth and roadmap; vendor-reported specifications." }, { "id": "huawei-ascend-2026", "title": "Huawei Connect 2026: Ascend supernode deployment update", "url": "https://www.huawei.com/cn/news/2026/9/hc-wang-keynote", "publisher": "Huawei", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2026-09-01", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official 2026 update states Ascend 950 supernodes have reached commercial scale; it does not independently establish availability of every 950 card SKU." } ], "references": [ { "id": "ref-huawei-ascend-1", "label": "Atlas 950 SuperPoD at MWC 2026", "url": "https://www.huawei.com/en/news/2026/3/mwc-superpod-ai", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-huawei-ascend-2", "label": "Atlas 950 SuperPoD at WAIC 2026", "url": "https://it-news.uk/posts/huawei-atlas-950-superpod-waic-2026/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-huawei-ascend-roadmap", "label": "Huawei Connect 2025 Ascend roadmap and architecture keynote", "url": "https://www.huawei.com/cn/news/2025/9/hc-xu-keynote-speech", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": "2025-09-18", "checked_at": "2026-11-06", "notes": "Official source for 950PR/DT architecture and vendor specifications." }, { "id": "ref-huawei-ascend-2026", "label": "Huawei Connect 2026 Ascend supernode deployment update", "url": "https://www.huawei.com/cn/news/2026/9/hc-wang-keynote", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": "2026-09-01", "checked_at": "2026-11-06", "notes": "Commercial deployment statement applies to 950 supernodes; individual SKU availability is not separately audited." } ] }, { "id": "cambricon", "display_name": "Cambricon (寒武纪)", "category": "China AI Accelerator Vendors", "directory_anchor": "Cambricon", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Cambricon_logo.png", "summary": "Cambricon develops MLU accelerators and the NeuWare software stack. This structured record covers the publicly documented MLU370-S4/S8 card family; newer roadmap or market-reported products remain unstructured until authoritative product specifications are available.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [ { "id": "mlu370-s4-s8", "name": "Cambricon MLU370-S4/S8 Accelerator Card", "product_type": "npu", "architecture": "Cambricon MLUarch03; chiplet-based architecture", "generation": "Siyuan 370", "family": "Cambricon MLU370", "process_node": "7nm", "market_segment": "Cloud AI inference and mixed AI workloads", "availability": "shipping", "form_factor": "PCIe Gen4 half-height, half-length single-slot accelerator card", "claim_ids": [ "mlu370-int8", "mlu370-fp16", "mlu370-bf16", "mlu370-fp32", "mlu370-memory", "mlu370-bandwidth", "mlu370-power" ], "compatibility_platform_ids": [ "cambricon" ] } ], "claims": [ { "id": "mlu370-int8", "subject_type": "product", "subject_id": "mlu370-s4-s8", "topic": "compute", "statement": "Cambricon lists 192 TOPS INT8 peak performance for MLU370-S4/S8.", "value": 192, "unit": "TOPS INT8", "scope": "Per accelerator card; vendor specification.", "claim_status": "vendor_reported", "evidence_ids": [ "cambricon-mlu370-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "board", "operation": "matrix", "precision": "INT8", "sparsity": "unspecified" } }, { "id": "mlu370-fp16", "subject_type": "product", "subject_id": "mlu370-s4-s8", "topic": "compute", "statement": "Cambricon lists 72 TFLOPS FP16 peak performance for MLU370-S4/S8.", "value": 72, "unit": "TFLOPS FP16", "scope": "Per accelerator card; vendor specification.", "claim_status": "vendor_reported", "evidence_ids": [ "cambricon-mlu370-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "board", "operation": "matrix", "precision": "FP16", "sparsity": "unspecified" } }, { "id": "mlu370-bf16", "subject_type": "product", "subject_id": "mlu370-s4-s8", "topic": "compute", "statement": "Cambricon lists 72 TFLOPS BF16 peak performance for MLU370-S4/S8.", "value": 72, "unit": "TFLOPS BF16", "scope": "Per accelerator card; vendor specification.", "claim_status": "vendor_reported", "evidence_ids": [ "cambricon-mlu370-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "board", "operation": "matrix", "precision": "BF16", "sparsity": "unspecified" } }, { "id": "mlu370-fp32", "subject_type": "product", "subject_id": "mlu370-s4-s8", "topic": "compute", "statement": "Cambricon lists 18 TFLOPS FP32 peak performance for MLU370-S4/S8.", "value": 18, "unit": "TFLOPS FP32", "scope": "Per accelerator card; vendor specification.", "claim_status": "vendor_reported", "evidence_ids": [ "cambricon-mlu370-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "board", "operation": "matrix", "precision": "FP32", "sparsity": "unspecified" } }, { "id": "mlu370-memory", "subject_type": "product", "subject_id": "mlu370-s4-s8", "topic": "memory_capacity", "statement": "Cambricon lists 24 GB / 48 GB LPDDR5 memory options for MLU370-S4/S8.", "value": "24 GB / 48 GB", "unit": "LPDDR5", "scope": "Per accelerator card; capacity varies by card variant, source does not map each capacity to S4 vs S8 in the same table.", "claim_status": "vendor_reported", "evidence_ids": [ "cambricon-mlu370-specs" ], "last_reviewed": "2026-11-06", "notes": "Variant capacity is preserved as a string because the official page does not explicitly map the two capacities to each SKU in the cited specification table." }, { "id": "mlu370-bandwidth", "subject_type": "product", "subject_id": "mlu370-s4-s8", "topic": "memory_bandwidth", "statement": "Cambricon lists 307.2 GB/s memory bandwidth for MLU370-S4/S8.", "value": 307.2, "unit": "GB/s", "scope": "Per accelerator card.", "claim_status": "vendor_reported", "evidence_ids": [ "cambricon-mlu370-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "board", "operation": "memory" } }, { "id": "mlu370-power", "subject_type": "product", "subject_id": "mlu370-s4-s8", "topic": "power", "statement": "Cambricon lists 75 W maximum thermal design power for MLU370-S4/S8.", "value": 75, "unit": "W TDP", "scope": "Per accelerator card.", "claim_status": "vendor_reported", "evidence_ids": [ "cambricon-mlu370-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "board", "operation": "power" } } ], "evidence": [ { "id": "cambricon-mlu370-specs", "title": "MLU370-S4/S8 accelerator card specifications", "url": "https://www.cambricon.com/index.php?a=lists&c=index&catid=367&m=content", "publisher": "Cambricon", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official Cambricon product specification page: MLUarch03, 7nm, 192 TOPS INT8, 72 TFLOPS FP16/BF16, 24GB/48GB LPDDR5, 307.2GB/s, PCIe Gen4 and 75W." } ], "references": [ { "id": "ref-cambricon-1", "label": "Siyuan 690 mass production", "url": "https://en.shuziqushi.com/new343300.html", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-cambricon-2", "label": "500,000 AI chips target for 2026", "url": "https://www.tomshardware.com/tech-industry/semiconductors/cambricon-targets-500000-ai-chips-in-2026-as-china-accelerates-domestic-hardware-push", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-cambricon-mlu370", "label": "Cambricon MLU370-S4/S8 product specifications", "url": "https://www.cambricon.com/index.php?a=lists&c=index&catid=367&m=content", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": null, "checked_at": "2026-11-06", "notes": "Official product specifications; 24GB/48GB capacity options retained without assigning each capacity to an individual card variant." } ] }, { "id": "biren", "display_name": "Biren Technology (壁仞科技)", "category": "China AI Accelerator Vendors", "directory_anchor": "Biren", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Biren_logo.png", "summary": "Biren develops general-purpose GPU-class accelerators for data-center AI training and inference. The BR100 family established its high-performance GPGPU direction; subsequent BR-series products and system offerings should be tracked by exact SKU and deployment status rather than treating the family as one device. The company listed in Hong Kong in January 2026 (6082.HK).", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-biren-1", "label": "Hong Kong listing", "url": "https://www.reuters.com/world/asia-pacific/china-ai-chipmaker-biren-surges-82-hong-kong-debut-kicking-off-2026-listings-2026-01-02/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-biren-2", "label": "Biren official site", "url": "https://www.birentech.com/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "moore-threads", "display_name": "Moore Threads (摩尔线程)", "category": "China AI Accelerator Vendors", "directory_anchor": "MooreThreads", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/MooreThreads_logo.png", "summary": "Moore Threads develops full-function GPUs for graphics and AI (MTT S-series) with the MUSA software stack. The company completed a large STAR Market IPO in late 2025 amid China’s domestic GPU push, targeting intelligent-computing centers and PC/GPU markets.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-moore-threads-1", "label": "Shanghai trading debut", "url": "https://www.cnbc.com/2025/12/05/china-nvidia-moore-threads-trading-debut-1-billion-listing-ipo-shanghai-gpu-enflame-biren.html", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "meta-x", "display_name": "MetaX (沐曦)", "category": "China AI Accelerator Vendors", "directory_anchor": "MetaX", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/MetaX_logo.png", "summary": "MetaX (沐曦) ships C-series GPUs for training and inference with the MXMACA software stack for AI clusters and intelligent-computing centers. After listing on STAR in Dec 2025, the company reported strong revenue growth into 2026 as domestic GPU demand rose.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-meta-x-1", "label": "MetaX doubles revenue", "url": "https://www.caixinglobal.com/2026-03-26/chinese-gpu-maker-metax-doubles-revenue-amid-push-for-domestic-chips-102427800.html", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "hygon", "display_name": "Hygon (海光) DCU", "category": "China AI Accelerator Vendors", "directory_anchor": "Hygon", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Hygon_logo.png", "summary": "Hygon’s Deep Computing Unit (DCU) accelerators are GPGPU-class chips widely used in China for large-model training and inference, paired with the DTK software stack. Hygon also ships x86 CPUs; the DCU line is the AI-relevant product for intelligent-computing centers.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-hygon-1", "label": "DeepSeek-V4 Day-0 adaptation", "url": "https://www.trendforce.com/news/2026/04/29/news-huawei-ascend-cambricon-and-hygon-completed-day-0-adaptation-to-deepseek-v4/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "iluvatar", "display_name": "Iluvatar CoreX (天数智芯)", "category": "China AI Accelerator Vendors", "directory_anchor": "Iluvatar", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Iluvatar_logo.png", "summary": "Iluvatar CoreX develops general-purpose GPU products for AI training and inference. Its public product portfolio spans the TianGai (天垓) training-GPU family, ZhiKai (智铠) inference products, and TongYang (彤央) edge-computing products. Product comparisons should be SKU-specific and distinguish announced roadmap items from shipping products.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-iluvatar-1", "label": "ixRT open-source components", "url": "https://github.com/Deep-Spark/iluvatar-corex-ixrt", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-iluvatar-2", "label": "DeepSparkInference", "url": "https://github.com/Deep-Spark/DeepSparkInference", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-iluvatar-3", "label": "Deep-Spark GitHub organization", "url": "https://github.com/Deep-Spark", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-iluvatar-4", "label": "CoreX software platform", "url": "https://www.iluvatar.com/software?fullCode=cpjs-rj-rjz", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "enflame", "display_name": "Enflame (燧原科技)", "category": "China AI Accelerator Vendors", "directory_anchor": "Enflame", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Enflame_logo.png", "summary": "Enflame develops CloudBlazer (云燧) GCU accelerators and systems for data-center AI training and inference. Its portfolio includes separate training and inference product directions; system offerings and product availability should be distinguished from silicon announcements and roadmap claims.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-enflame-1", "label": "torch-gcu open-source repository", "url": "https://github.com/EnflameTechnology/torch-gcu", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-enflame-2", "label": "Enflame official site", "url": "https://www.enflame-tech.com/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "horizon", "display_name": "Horizon Robotics (地平线)", "category": "China AI Accelerator Vendors", "directory_anchor": "Horizon", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Horizon_Robotics_logo.png", "summary": "Horizon Robotics (地平线) is a leading China automotive AI SoC vendor. Journey-series chips (through Journey 6 with BPU Nash) power L2+ assisted driving in many passenger vehicles, with increasing Transformer support for BEV/occupancy and end-to-end driving models.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-horizon-1", "label": "Journey 6 / BPU Nash", "url": "https://www.horizon.auto/en/solutions/horizon-journey/horizon-journey6", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "black-sesame", "display_name": "Black Sesame Technologies (黑芝麻智能)", "category": "China AI Accelerator Vendors", "directory_anchor": "BlackSesame", "logo_url": "https://github.com/basicmi/AI-Chip/raw/master/resource/Blacksesame_logo.png", "summary": "Black Sesame Technologies (黑芝麻智能) designs automotive-grade ADAS/AD SoCs (Huashan family). Hong Kong-listed in 2024, the company focuses on safety-certified L2+/L3 platforms; A1000-family chips are reported in mass-production vehicles, with A2000 extending toward higher-performance and cross-domain AI.", "profile_status": "not_reviewed", "last_reviewed": null, "products": [], "claims": [], "evidence": [], "references": [ { "id": "ref-black-sesame-1", "label": "Huashan A1000 / A2000 path", "url": "https://www.blacksesame.com/en/huashan-a1000/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-2", "label": "MLIR", "url": "https://mlir.llvm.org/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-3", "label": "OpenXLA / XLA", "url": "https://openxla.org/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-4", "label": "Apache TVM", "url": "https://tvm.apache.org/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-5", "label": "IREE", "url": "https://iree.dev/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-6", "label": "TorchInductor", "url": "https://pytorch.org/docs/stable/torch.compiler.html", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-7", "label": "Triton", "url": "https://github.com/triton-lang/triton", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-8", "label": "TileLang", "url": "https://github.com/tile-ai/tilelang", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-9", "label": "TIRx", "url": "https://tvm.apache.org/docs/tirx/overview.html", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-10", "label": "Helion", "url": "https://github.com/pytorch/helion", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-11", "label": "CuTe / CUTLASS DSL", "url": "https://github.com/NVIDIA/cutlass", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-12", "label": "JAX Pallas", "url": "https://docs.jax.dev/en/latest/pallas/index.html", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-13", "label": "FlashAttention", "url": "https://github.com/Dao-AILab/flash-attention", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-14", "label": "FlashInfer", "url": "https://github.com/flashinfer-ai/flashinfer", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-15", "label": "DeepGEMM", "url": "https://github.com/deepseek-ai/DeepGEMM", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-16", "label": "AITer", "url": "https://github.com/ROCm/aiter", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-17", "label": "Composable Kernel", "url": "https://github.com/ROCm/composable_kernel", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-18", "label": "vLLM", "url": "https://github.com/vllm-project/vllm", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-19", "label": "SGLang", "url": "https://github.com/sgl-project/sglang", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-20", "label": "TensorRT-LLM", "url": "https://github.com/NVIDIA/TensorRT-LLM", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-21", "label": "MLC-LLM", "url": "https://github.com/mlc-ai/mlc-llm", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-22", "label": "llama.cpp", "url": "https://github.com/ggml-org/llama.cpp", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-23", "label": "NVIDIA Dynamo", "url": "https://github.com/ai-dynamo/dynamo", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-24", "label": "llm-d", "url": "https://github.com/llm-d/llm-d", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-25", "label": "Mooncake", "url": "https://github.com/kvcache-ai/Mooncake", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-26", "label": "NIXL", "url": "https://github.com/ai-dynamo/nixl", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-27", "label": "NCCL", "url": "https://github.com/NVIDIA/nccl", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-28", "label": "RCCL", "url": "https://github.com/ROCm/rccl", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-29", "label": "MLPerf / MLCommons", "url": "https://mlcommons.org/benchmarks/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-30", "label": "SemiAnalysis InferenceX", "url": "https://inferencex.semianalysis.com/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-31", "label": "KernelBench", "url": "https://github.com/ScalingIntelligence/KernelBench", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-32", "label": "NCCL Tests", "url": "https://github.com/NVIDIA/nccl-tests", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-33", "label": "OSU Micro-Benchmarks", "url": "https://mvapich.cse.ohio-state.edu/benchmarks/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-34", "label": "AI Chip Paper List", "url": "https://birenresearch.github.io/AIChip_Paper_List/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-35", "label": "Neural Network Accelerator Comparison", "url": "https://nicsefc.ee.tsinghua.edu.cn/projects/neural-network-accelerator/", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-36", "label": "Tutorial on Hardware Architectures for Deep Neural Networks", "url": "http://eyeriss.mit.edu/tutorial.html", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-37", "label": "#1", "url": "https://mp.weixin.qq.com/s/SbX5yz5d3GXaLcl15DO6OQ", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-38", "label": "#2", "url": "https://mp.weixin.qq.com/s/zvgDgKpIMIRLFUEW0fFOeg", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-39", "label": "#3", "url": "https://mp.weixin.qq.com/s/CKHs5yblcMur4h2BwUBICw", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-40", "label": "#4", "url": "https://mp.weixin.qq.com/s/hFnHhaWWYTFRUsD3HlMbLw", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-41", "label": "TPU vs GPU vs Cerebras vs Graphcore", "url": "https://khairy2011.medium.com/tpu-vs-gpu-vs-cerebras-vs-graphcore-a-fair-comparison-between-ml-hardware-3f5a19d89e38", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-42", "label": "download", "url": "https://cloud.tsinghua.edu.cn/f/9aa0a4f0a5684cc48495/?dl=1", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-43", "label": "Google Drive", "url": "https://drive.google.com/open?id=1ieDm0bpjVWl5MnSESRs92EcmoSzG5vcm", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." }, { "id": "ref-black-sesame-44", "label": "External reference", "url": "http://www.reliablecounter.com", "source_type": "unknown", "review_status": "unreviewed", "published_at": null, "checked_at": null, "notes": "Carried over from directory.md. Source type, publication date and claim-level support have not yet been audited." } ] }, { "id": "rebellions", "display_name": "Rebellions — AI inference NPUs", "category": "Startups", "directory_anchor": "Rebellions", "logo_url": "https://rebellions.ai/favicon.ico", "summary": "Rebellions develops inference-focused NPUs. ATOM and ATOM-Max represent its first-generation products; REBEL-Quad is a chiplet-based UCIe-Advanced follow-on aimed at larger data-center inference systems.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [ { "id": "rebellions-atom", "name": "Rebellions ATOM", "product_type": "npu", "architecture": "Inference-optimized NPU", "generation": "ATOM first generation", "family": "Rebellions ATOM", "market_segment": "Enterprise and small data-center inference", "availability": "production", "form_factor": "Single-slot PCIe Gen5 accelerator card", "claim_ids": [ "atom-fp16", "atom-int8", "atom-memory", "atom-bandwidth", "atom-power" ], "availability_history": [ { "status": "production", "effective_at": "2025-09-30", "evidence_id": "rebellions-roadmap", "notes": "Rebellions states ATOM and ATOM-Max are in mass production." } ] }, { "id": "rebellions-rebel-quad", "name": "Rebellions REBEL-Quad", "product_type": "asic", "architecture": "Chiplet-based UCIe-Advanced AI inference accelerator", "generation": "Second generation", "family": "Rebellions REBEL", "market_segment": "Large-scale data-center inference", "availability": "announced", "form_factor": "Chiplet-based accelerator", "claim_ids": [ "rebelquad-hbm", "rebelquad-architecture" ], "availability_history": [ { "status": "announced", "effective_at": "2025-08", "evidence_id": "rebellions-roadmap", "notes": "REBEL-Quad introduced in August 2025; exact day not stated in linked announcement." } ] } ], "claims": [ { "id": "atom-fp16", "subject_type": "product", "subject_id": "rebellions-atom", "topic": "compute", "statement": "Rebellions lists 32 TFLOPS FP16 for ATOM.", "value": 32, "unit": "TFLOPS FP16", "scope": "Per ATOM accelerator card.", "claim_status": "vendor_reported", "evidence_ids": [ "rebellions-atom-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "board", "operation": "matrix", "precision": "FP16", "sparsity": "unspecified" } }, { "id": "atom-int8", "subject_type": "product", "subject_id": "rebellions-atom", "topic": "compute", "statement": "Rebellions lists 128 TOPS INT8 for ATOM.", "value": 128, "unit": "TOPS INT8", "scope": "Per ATOM accelerator card.", "claim_status": "vendor_reported", "evidence_ids": [ "rebellions-atom-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "board", "operation": "matrix", "precision": "INT8", "sparsity": "unspecified" } }, { "id": "atom-memory", "subject_type": "product", "subject_id": "rebellions-atom", "topic": "memory_capacity", "statement": "ATOM provides 16 GB GDDR6.", "value": 16, "unit": "GB GDDR6", "scope": "Per accelerator card.", "claim_status": "vendor_reported", "evidence_ids": [ "rebellions-atom-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "board", "operation": "memory" } }, { "id": "atom-bandwidth", "subject_type": "product", "subject_id": "rebellions-atom", "topic": "memory_bandwidth", "statement": "ATOM provides 256 GB/s memory bandwidth.", "value": 256, "unit": "GB/s", "scope": "Per accelerator card.", "claim_status": "vendor_reported", "evidence_ids": [ "rebellions-atom-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "board", "operation": "memory" } }, { "id": "atom-power", "subject_type": "product", "subject_id": "rebellions-atom", "topic": "power", "statement": "ATOM maximum power consumption is 85 W.", "value": 85, "unit": "W", "scope": "Per accelerator card.", "claim_status": "vendor_reported", "evidence_ids": [ "rebellions-atom-specs" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "board", "operation": "power" } }, { "id": "rebelquad-hbm", "subject_type": "product", "subject_id": "rebellions-rebel-quad", "topic": "memory_capacity", "statement": "Rebellions describes REBEL-Quad with 144 GB HBM3E.", "value": 144, "unit": "GB HBM3E", "scope": "Per REBEL-Quad accelerator; company announcement.", "claim_status": "vendor_reported", "evidence_ids": [ "rebellions-roadmap" ], "last_reviewed": "2026-11-06", "metric_context": { "metric_type": "specification", "measurement_scope": "chip", "operation": "memory" } }, { "id": "rebelquad-architecture", "subject_type": "product", "subject_id": "rebellions-rebel-quad", "topic": "architecture", "statement": "REBEL-Quad uses a chiplet-based UCIe-Advanced architecture.", "scope": "Product architecture as described by Rebellions; no public full die/package specification.", "claim_status": "vendor_reported", "evidence_ids": [ "rebellions-roadmap" ], "last_reviewed": "2026-11-06" } ], "evidence": [ { "id": "rebellions-atom-specs", "title": "ATOM product specifications", "url": "https://rebellions.ai/rebellions-product/rbln-ca22/", "publisher": "Rebellions", "source_type": "vendor_primary", "independence": "vendor", "published_at": null, "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official ATOM product page: 32 TFLOPS FP16, 128 TOPS INT8, 16GB GDDR6, 256GB/s and 85W." }, { "id": "rebellions-roadmap", "title": "Rebellions raises $250M to advance next-generation AI infrastructure", "url": "https://rebellions.ai/newsroom/rebellions-raises-250-million-to-advance-the-next-generation-ai-infrastructure-backed-by-arm-and-samsung/", "publisher": "Rebellions", "source_type": "vendor_primary", "independence": "vendor", "published_at": "2025-09-30", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Official announcement: ATOM and ATOM-Max in mass production; REBEL-Quad introduced in August 2025, chiplet-based UCIe-Advanced with 144GB HBM3E." } ], "references": [ { "id": "ref-rebellions-atom-specs", "label": "ATOM product specifications", "url": "https://rebellions.ai/rebellions-product/rbln-ca22/", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": null, "checked_at": "2026-11-06", "notes": "Per-card specifications." }, { "id": "ref-rebellions-roadmap", "label": "REBEL-Quad product roadmap announcement", "url": "https://rebellions.ai/newsroom/rebellions-raises-250-million-to-advance-the-next-generation-ai-infrastructure-backed-by-arm-and-samsung/", "source_type": "vendor_primary", "review_status": "reviewed", "published_at": "2025-09-30", "checked_at": "2026-11-06", "notes": "Architecture and HBM capacity are vendor-reported; production timing is not inferred." } ] }, { "id": "ampere", "display_name": "Ampere Computing — Arm server CPUs", "category": "Acquired / Legacy", "directory_anchor": "Ampere", "logo_url": "https://amperecomputing.com/favicon.ico", "summary": "Ampere develops Arm-based server CPUs for cloud and AI infrastructure, including AmpereOne and AmpereOne M. SoftBank completed its $6.5 billion acquisition on 25 November 2025; Ampere remains an operating subsidiary and continues publishing product and deployment updates.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [], "claims": [ { "id": "ampere-softbank-ownership", "subject_type": "company", "subject_id": "ampere", "topic": "availability", "statement": "SoftBank completed its acquisition of Ampere on 25 November 2025; Ampere continues operating as a wholly owned subsidiary.", "scope": "Corporate ownership and operating status; reviewed 2026-11-06.", "claim_status": "source_confirmed", "evidence_ids": [ "ampere-softbank-acquisition-completed" ], "last_reviewed": "2026-11-06" } ], "evidence": [ { "id": "ampere-softbank-acquisition-completed", "title": "Completion of Acquisition of Ampere Computing Holdings LLC", "url": "https://group.softbank/en/news/press/20251126", "publisher": "SoftBank Group", "source_type": "company_primary", "independence": "vendor", "published_at": "2025-11-26", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "SoftBank says it completed the acquisition of all Ampere equity interests on 25 November 2025; Ampere became a wholly owned subsidiary." }, { "id": "ampere-2026-product-updates", "title": "Ampere press releases and product updates", "url": "https://amperecomputing.com/press/1", "publisher": "Ampere Computing", "source_type": "company_primary", "independence": "vendor", "published_at": "2026-03-19", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "Ampere's official press index lists 2026 AmpereOne / AmpereOne M deployments, confirming ongoing activity under the Ampere brand." } ], "references": [ { "id": "ref-ampere-softbank-acquisition", "label": "SoftBank completes Ampere acquisition", "url": "https://group.softbank/en/news/press/20251126", "source_type": "company_primary", "review_status": "reviewed", "published_at": "2025-11-26", "checked_at": "2026-11-06", "notes": "SoftBank says it completed the acquisition of all Ampere equity interests on 25 November 2025; Ampere became a wholly owned subsidiary." }, { "id": "ref-ampere-2026-products", "label": "Ampere 2026 product and deployment updates", "url": "https://amperecomputing.com/press/1", "source_type": "company_primary", "review_status": "reviewed", "published_at": "2026-03-19", "checked_at": "2026-11-06", "notes": "Ampere's official press index lists 2026 AmpereOne / AmpereOne M deployments, confirming ongoing activity under the Ampere brand." } ], "corporate_status": { "ownership_status": "wholly_owned_subsidiary", "operating_status": "active", "parent_company": "SoftBank Group", "effective_date": "2025-11-25", "transaction_type": "acquisition", "notes": "Wholly owned subsidiary of SoftBank; Ampere continues to operate under its own name and ship AmpereOne family products.", "evidence_ids": [ "ampere-softbank-acquisition-completed", "ampere-2026-product-updates" ] } }, { "id": "untether-ai", "display_name": "Untether AI — speedAI (discontinued)", "category": "Acquired / Legacy", "directory_anchor": "UntetherAI", "logo_url": "https://www.untether.ai/", "summary": "Untether AI developed at-memory AI inference accelerators (speedAI) and the imAIgine SDK. In June 2025 it entered a strategic transaction with AMD that transferred an engineering team; Untether said it would stop supplying and supporting its products. Treat the company as ceased operations, not as an active AMD product line.", "profile_status": "partially_reviewed", "last_reviewed": "2026-11-06", "products": [], "claims": [ { "id": "untether-ai-ceased-operations", "subject_type": "company", "subject_id": "untether-ai", "topic": "availability", "statement": "Untether AI stopped supplying speedAI products and supporting imAIgine SDK after a 2025 AMD engineering-team acqui-hire; the sources do not establish an acquisition of the company or its IP.", "scope": "Corporate ownership and operating status; reviewed 2026-11-06.", "claim_status": "source_confirmed", "evidence_ids": [ "untether-amd-team-acquihire" ], "last_reviewed": "2026-11-06" } ], "evidence": [ { "id": "untether-amd-team-acquihire", "title": "AMD acquires team behind AI chip startup Untether AI", "url": "https://www.crn.com/news/components-peripherals/2025/exclusive-amd-acquires-team-behind-ai-chip-startup-untether-ai", "publisher": "CRN reporting AMD and Untether statements", "source_type": "independent_media", "independence": "independent", "published_at": "2025-06-05", "checked_at": "2026-11-06", "review_status": "reviewed", "notes": "AMD confirmed a strategic agreement to acquire a team of AI hardware/software engineers. Untether stated it would no longer supply speedAI products or support imAIgine SDK; this is an acqui-hire, not evidence AMD acquired the company or its IP." } ], "references": [ { "id": "ref-untether-amd-acquihire", "label": "Untether AI ends product supply and support after AMD team transaction", "url": "https://www.crn.com/news/components-peripherals/2025/exclusive-amd-acquires-team-behind-ai-chip-startup-untether-ai", "source_type": "independent_media", "review_status": "reviewed", "published_at": "2025-06-05", "checked_at": "2026-11-06", "notes": "AMD confirmed a strategic agreement to acquire a team of AI hardware/software engineers. Untether stated it would no longer supply speedAI products or support imAIgine SDK; this is an acqui-hire, not evidence AMD acquired the company or its IP." } ], "corporate_status": { "ownership_status": "ceased_operations", "operating_status": "ceased", "team_acquired_by": "AMD", "effective_date": "2025-06-05", "transaction_type": "acqui_hire", "notes": "AMD acquired an engineering team; Untether AI's own statement says its product supply and SDK support ended. No claim is made that AMD acquired all Untether IP or corporate equity.", "evidence_ids": [ "untether-amd-team-acquihire" ] } } ], "comparison_policy": { "precision_must_match": true, "sparsity_must_match": true, "measurement_scope_must_match": true, "metric_type_must_match": true, "system_and_chip_metrics_must_not_be_mixed": true, "source_units_must_be_preserved": true, "notes": "Do not compare peak compute across different precisions or dense/sparse modes. Do not mix chip, module, board, server, rack, pod or cluster scope. Keep theoretical/vendor specifications separate from measured results. Preserve source units; any UI conversion must retain the original value and unit." } }